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SOLVING SECOND ORDER DIFFERENTIAL EQUATIONS IN QUANTUM MECHANICS BYORDER REDUCTION

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Acta Mathematica Scientia 2003年第2期23卷 274-288页

作者： C.Ted Chen grace semiconductor Manufacturing corporation 2nd Floor

Solving the famous Hermite, Legendre, Laguerre and Chebyshev equations requires different techniques of unique character for each equation. By reducing these differential equations of second order to a common solvable differential equation of first order, a simple common solution is provided to cover all the existing standard solutions of these named equations. It is easier than the method of generating functions and more powerful than the Probenius method of power series.

关键词： Second order differential equations quantum mechanics common solution

Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization

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Tsinghua Science and Technology 2007年第6期12卷 741-746页

作者：潘立阳孙磊伍冬陈军许军朱钧 Institute of Microelectronics Tsinghua University semiconductor manufacture International corporation

A 4 Mb embedded silicon-oxide-nitride-oxide-silicon （SONOS） memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 105 cycles and a data retention time of at least 10 years.

关键词： flash memory silicon-oxide-nitride-oxide-silicon (SONOS) charge distribution endurance retention

Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost

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Journal of semiconductors 2009年第7期30卷 80-82页

作者：单毅何军黄文毅 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences grace semiconductor Manufacturing corporation

A new thyristor is proposed and realized in the foundry＇s 0.18-μm CMOS process for electrostatic dis-charge（ESD） *** extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor（ULVT thyristor） has a trigger voltage as low as 6.7 V and an ESD robustness exceeding 50 mA/μm, which enables effective ESD *** with the traditional medium-voltage-trigger thyristor（MVT thyristor）, the new structure not only has a lower trigger voltage, but can also provide better ESD protection under both positive and negative ESD zapping conditions.

关键词： thyristor electro-static discharge ultra-low-voltage-trigger positive negative

A novel 2-T structure memory device using a Si nanodot for embedded application

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Journal of semiconductors 2011年第12期32卷 86-90页

作者：杨潇楠王永张满红霍宗亮刘璟张博刘明 Laboratory of Nano-Fabrication and Novel Devices Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences grace semiconductor Manufacturing corporation

Performance and reliability ofa 2 transistor Si nanocrystal nonvolatile memory （NVM） are investigated. A good performance of the memory cell has been achieved, including a fast program/erase （P/E） speed under low voltages, an excellent data retention （maintaining for 10 years） and good endurance with a less threshold voltage shift of less than 10% after 104 P/E cycles. The data show that the device has strong potential for future embedded NVM applications.

关键词： nonvolatile memory nanocrystal reliability

An effective approach to improve split-gate flash product data retention

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Journal of semiconductors 2017年第10期38卷 107-110页

作者： Dailong Wei Zigui Cao Zhilin Tang Department of Process Integration Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Data retention is one of the most important reliability characteristics of split-gate ***,many efforts were made to improve data retention of split-gate *** experiments,it was found that higher chlorine concentration produced in FGSP2 oxide deposition can induce worse data ***,reducing chlorine concentration is an effective approach to improve data retention for split-gate flash *** RTO annealing between FGSP2 oxide deposition and FGSP2 etching could reduce chlorine concentration,and improve FGSP2 oxide film quality,and then get better data retention.

关键词： split-gate flash data retention RTO anneal

Body-contact self-bias effect in partially depleted SOI-CMOS and alternatives to suppress floating body effect

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Journal of semiconductors 2011年第2期32卷 33-37页

作者：周建华高明辉彭树根邹世昌 grace semiconductor Manufacturing corporation Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences

As SOI-CMOS technology nodes reach the tens ofnanometer regime, body-contacts become more and more ineffective to suppress the floating body effect. In this paper, self-bias effect as the cause for this failure is analyzed and discussed in depth with respect to different structures and conditions. Other alternative approaches to suppressing the floating body effect are also introduced and discussed.

关键词： partially depleted SOI-CMOS floating body effect hot-carriers kink-effect gate oxide tunneling

Overlay mark optimization for thick-film resist overlay metrology

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Journal of semiconductors 2009年第6期30卷 142-146页

作者：朱亮李杰周从树顾以理杨华岳 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences grace semiconductor Manufacturing corporation

For thick resist implant layers,such as a high voltage P well and a deep N well,systematic and uncorrectable overlay residues brought about by the tapered resist profiles were *** was found that the tapered profile is closely related to the pattern *** solutions of the manufacturing problem include hardening the film solidness or balancing the exposure *** this paper,instead of focusing on the process change methodology,we intend to solve the issue of the overlay metrology error from the perspective of the overlay mark *** on the comparison of the overlay performances between the proposed overlay mark and the original design,it is shown that the optimized overlay mark target achieves better performance in terms of profiles,dynamic precision,tool induced shift（TIS）,and ***,five types of overlay marks with dummy bars are studied,and a recommendation for the overlay marks is given.

关键词： overlay metrology error dynamic precision tool induced shift statistical process control depth of focus exposure latitude

Role of CF_2 in the etching of SiO_2,Si_3N_4 and Si in fluorocarbon plasma

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Journal of semiconductors 2009年第3期30卷 30-34页

作者：陈乐乐朱亮徐昕睿李东霞蔡辉包大勇 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences grace semiconductor Manufacturing corporation

The CF2 density and etch rate of SiO2, Si3N4 and Si are investigated as a function of gas pressure and O2 flow rate in fluorocarbon plasma. As the pressure increases, the self-bias voltage decreases whereas the SiO2 etch rate increases. Previous study has shown that SiO2 etch rate is proportional to the self-bias voltage. This result indicates that other etching parameters contribute to the SiO2 etching. Generally, the CF2 radical is considered as a precursor for fluorocarbon layer formation. At a given power, defluorination of fluorocarbon under high-energy ion bombardment is a main source of fluorine for SiO2 etching. When more CF2 radical in plasma, SiO2 etch rate is increased because more fluorine can be provided. In this case, CF2 is considered as a reactant for SiO2 etching. The etch rate of Si3N4 and Si is mainly determined by the polymer thickness formed on its surface which is dominated by the CF2 density in plasma. Etching results obtained by varying O2 flow rate also support the proposition.

关键词： CF2 SiO2 etching fluorocarbon film

Characterization of the triple-gate flash memory endurance degradation mechanism

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Journal of semiconductors 2009年第1期30卷 19-22页

作者：曹子贵孙凌李嘉秩 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Graduate University of the Chinese Academy of Sciences grace semiconductor Manufacturing corporation

Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash memory have been detected and analyzed using a UV erasure method. Different from the commonly degradation phenomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in hornshaped SuperFlash does not occur in the triple-gate flash cell This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash cell Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.

关键词： Fowler-Nordheim tunneling endurance traps UV erasure