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Design and Tool Flow of a Reconfigurable asynchronous Neural Network Accelerator

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Tsinghua Science and Technology 2021年第5期26卷 565-573页

作者： Jilin Zhang Hui Wu Weijia Chen Shaojun Wei Hong Chen the Institute of Microelectronics Tsinghua National Laboratory for Information Science and Technologyand Beijing Engineering Center of Technology and research on Wireless Medical and Health SystemTsinghua UniversityBeijing 100084China

Convolutional Neural Networks(CNNs)are widely used in computer vision,natural language processing,and so on,which generally require low power and high efficiency in real ***,energy efficiency has become a critical indicator of CNN *** that asynchronous circuits have the advantages of low power consumption,high speed,and no clock distribution problems,we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor(CMOS)*** the absence of a commercial design tool flow for asynchronous circuits,we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation(EDA)*** also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct *** accelerator for handwriting recognition network(LeNet-5 model)is *** test results show that the asynchronous accelerator has 30%less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W,which is 12%higher than that of the synchronous chip.

关键词： Convolutional Neural Network(CNN)accelerator asynchronous circuit energy efficiency adaptive delay matching asynchronous design flow

An asynchronous Adaptive Priority Round-Robin Arbiter Based on Four-Phase Dual-rail Protocol

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Chinese Journal of Electronics 2015年第1期24卷 1-7页

作者： YANG Yintang WU Ruizhen ZHANG Li ZHOU Duan School of Microelectronics Xidian University School of Computer Science and Technology Xidian University

An asynchronous Adaptive priority roundrobin arbiter(APRA) based on four-phase dual-rail protocol is proposed. Combining the advantages of synchronous and asynchronous circuits, it provides the required bandwidth allocation on basis of arbitration fairness and works in synchronous So C. In the Nonidling and nonpreemptive(NINP) model, simulations and verifications are made. The results show that the speed of the proposed arbiter is improved by 18%–50.4% and the dynamic and static power is reduced by 8.4%–46.2% and 81.8%–90.9% respectively compared with the commonly-used Fixed priority(FP),Round-Robin(RR) and Lottery arbiters. The proposed arbiter is better in output bandwidth allocation and it also has advantages in speed and power. Furthermore, it is easy in reconfiguration, strong in practicability and low in complexity of system integration and suits various extreme communication traffics.

关键词： Arbiter asynchronous circuit Fourphase dual-rail protocol System-on-chip(So C).

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection

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Science in China(Series F) 2008年第7期51卷 975-984页

作者： QIAO Fei YANG HuaZhong HUANG Gang WANG Hui NICS Group Department of Electronic Engineering Tsinghua University Beijing 100084 China

A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.

关键词： low power circuit low-swing interface differential signaling tapered-buffer interconnect asynchronous circuit

A self-circulation structure for pipeline control

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Journal of Harbin Institute of Technology(New Series) 2009年第6期16卷 771-775页

作者：王兵彭瑞华王琴 Dept. of Computer Science Shanghai Jiaotong University Shanghai Research Center AMD Corporation Institute of Microelectronics Shanghai Jiaotong University

This paper proposes a circuit structure which can be used for both synchronous and asynchronous pipeline control. It is a self-circulation structure with embedded delay network, and a pipeline can be controlled by this structure with the interconnection of adjacent stages. This paper first proposes a basic circuit structure, then a linear pipeline is designed with self-circulation structure. The performance of linear pipeline is analyzed, and a 16-bit digital signal processor (DSP) with the structure is designed to prove the validity of the structure. Results show that about 10%-15% power consumption is saved with self-circulation structure compared with synchronous counterpart, while almost the same performance is achieved.

关键词： pipeline self-circulation timing analysis asynchronous circuit

Low Latency High Throughout Circular asynchronous FIFO

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Tsinghua Science and Technology 2008年第6期13卷 812-816页

作者：肖勇周润德 Institute of Microelectronics Tsinghua University

This paper describes a circular first in first out （FIFO） and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipelines, this FIFO＇s cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase with the number of FIFO stages. Single-track asynchronous protocols are used to simplify the FIFO controller design, with only three C-gates needed in each cell controller, which substantially reduces the area. Simulations with the TSMC 0.25 μm CMOS logic process show that the latency of the 4-stage FIFO is less than 581 ps and the throughput is higher than 2.2 GHz.

关键词： asynchronous circuit asynchronous first in first out (FIFO) circular systems on a chip (SOC) global asynchronous local synchronous (GALS)

An asynchronous 32×8-Bit Multiplier Based on LDCVSPG Logic

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Wuhan University Journal of Natural Sciences 2007年第2期12卷 294-298页

作者： ZHONG Xiongguang RONG Mengtian School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai 200030 China

An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate （LDCVSPG） logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation （CSMC＇s） 0.6μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.

关键词： asynchronous circuit LDCVSPG array multiplier 4-phase dual-rail protocol