An Asynchronous 32×8-Bit Multiplier Based on LDCVSPG Logic

作     者：ZHONG Xiongguang RONG Mengtian 

作者机构：School of Electronic Information and Electrical Engineering Shanghai Jiao Tong University Shanghai 200030 China 

出 版 物：《Wuhan University Journal of Natural Sciences》 (武汉大学学报（自然科学英文版）)

年 卷 期：2007年第12卷第2期

页      面：294-298页

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Supported by the National High Technology Research and Development Program of China (2001AA141040) 

主　　题：asynchronous circuit LDCVSPG array multiplier 4-phase dual-rail protocol 

摘      要：An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate （LDCVSPG） logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation （CSMC＇s） 0.6μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.