Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection

作     者：QIAO Fei YANG HuaZhong HUANG Gang WANG Hui 

作者机构：NICS Group Department of Electronic Engineering Tsinghua University Beijing 100084 China 

出 版 物：《Science in China(Series F)》 (中国科学（F辑英文版）)

年 卷 期：2008年第51卷第7期

页      面：975-984页

核心收录：

学科分类：0810[工学-信息与通信工程] 0808[工学-电气工程] 080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：the 973 Program of China (Grant No.G1999032903) the National Science Fund for Distinguished Young Scholars (Grant No.60025101) the Major Program of National Natural Science Foundation of China (Grant No.90707002) 

主　　题：low power circuit low-swing interface differential signaling tapered-buffer interconnect asynchronous circuit 

摘      要：A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.