Low Latency High Throughout Circular Asynchronous FIFO

作     者：肖勇 周润德 

作者机构：Institute of MicroelectronicsTsinghua University 

出 版 物：《Tsinghua Science and Technology》 (清华大学学报（自然科学版（英文版）)

年 卷 期：2008年第13卷第6期

页      面：812-816页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Supported by the National Key Basic Research and Development(973) Program of China (No. 2006CB302700) the National High-Tech Research and Development (863) Program of China (No.2007AA01Z2B3) 

主　　题：asynchronous circuit asynchronous first in first out (FIFO) circular systems on a chip (SOC) global asynchronous local synchronous (GALS) 

摘      要：This paper describes a circular first in first out （FIFO） and its protocols which have a very low latency while still maintaining high throughput. Unlike the existing serial FIFOs based on asynchronous micropipelines, this FIFO＇s cells communicate directly with the input and output ports through a common bus, which effectively eliminates the data movement from the input port to the output port, thereby reducing the latency and the power consumption. Furthermore, the latency does not increase with the number of FIFO stages. Single-track asynchronous protocols are used to simplify the FIFO controller design, with only three C-gates needed in each cell controller, which substantially reduces the area. Simulations with the TSMC 0.25 μm CMOS logic process show that the latency of the 4-stage FIFO is less than 581 ps and the throughput is higher than 2.2 GHz.