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An Improved Planar Module Automatic Layout Method for Large Number of Dies

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CES Transactions on Electrical Machines and Systems 2017年第4期1卷 411-417页

作者： Puqi Ning Xuhui Wen Lei Li Han Cao Institute of Electrical engineering Chinese Academy of SciencesBeijing100190 China Collaborative Innovation center of Electric Vehicles in Beijing

The layout of power modules is one of the key points in power module design,especially for silicon carbide module,which may parallel more devices compared with silicon *** this paper,along with the design example,a improved layout design method for planar power modules is *** practical considerations and implementations are also introduced in the optimization of module layout design.

关键词： Multi-chip module packaging.

Highly Efficient and Linear Class E SiGe power Amplifier Design

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Highly Efficient and Linear Class E SiGe Power Amplifier Des...

Comparison between SiC- and Si-Based Inverters for Photovoltaic power Generation Systems

2006 8th International Conference on Solid-State and Integrated Circuit technology

作者： Donald Y.C.Lie Jeremy D.Popp Jason F.Rowland Annie H.Yang Feipeng Wang Don Kimball Dynamic research Corporation(DRC) San DiegoCA SPAWAR System center San DiegoCA Department of Electrical and Computer engineering University of CaliforniaSan Diego(UCSD)La JollaCA

ISBN: (纸本)1424401607

＜正＞This paper discusses the design of monolithic RF broadband Class E SiGe power amplifiers（PAs） that are highly efficient and ***-pull measurement data on IBM 7HP SiGe power devices have been made at 900MHz and 2.4GHz and monolithic class E PAs have been designed using these devices to achieve highest power-added-efficiency（PAE） at these *** is found that high PAE can be achieved for monolithic single-stage Class E PAs designed using high-breakdown SiGe transistors at～65%（900MHz） and～40%（2.4GHz）, respectively,which are roughly～10%lower than the device’s maximum PAE values obtained by load-pull tests under optimal off-chip matching *** have also demonstrated that monolithic SiGe class E PAs can be successfully linearized using an open-loop envelope tracking（ET） technique as their output spectra pass the stringent EDGE transmit mask with margins, achieving overall PAE of 44.4%for the linearized PA system that surpasses the ＜30%PAE with commercially available GaAs Class AB PAs for EDGE applications. These promising results indicate the feasibility of realizing true single-chip wireless transceivers with on-chip RF SiGe PAs for spectrally-efficient non-constant-envelope modulation schemes.

关键词： silicon germanium protactinium load-pull MONOLITHIC power amplifiers PUBLIC ADDRESS SYSTEM telecommunication standards cellular radio

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Journal of power and Energy engineering 2017年第1期5卷 30-40页

作者： Yuji Ando Yasuhiro Shirahata Takeo Oku Taisuke Matsumoto Yuya Ohishi Masashi Yasuda Akio Shimono Yoshikazu Takeda Mikio Murozono Department of Materials Science The University of Shiga Prefecture Shiga Japan Collaborative research center The University of Shiga Prefecture Shiga Japan Kyoshin Electric Company Limited Kyoto Japan Clean Venture 21 Corporation Kyoto Japan

100-W class power storage systems were developed, which comprised spherical Si solar cells, a maximum power point tracking charge control-ler, a lithium-ion battery, and one of two different types of direct current (DC)-alter- nating current (AC) converters. One inverter used SiC met-al-oxide-semicon-ductor field-effect transistors (MOSFETs) as switching devices while the other used Si MOSFETs. In these 100-W class inverters, the ON resistance was considered to have little influence on the efficiency. Nevertheless, the SiC-based inverter exhibited an approximately 3% higher DC-AC conversion efficiency than the Si-based inverter. power loss analysis indicated that the higher efficiency resulted predominantly from lower switching and reverse recovery losses in the SiC MOSFETs compared with in the Si MOSFETs.

关键词： silicon carbide Solar Cell Inverter Photovoltaic Device Maximum power Point Tracking Lithium-Ion Battery

基于非等径双球堆积模型和蒙特卡罗仿真模拟的纳米铜烧结互连机理分析

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焊接学报 2021年第3期42卷 7-13,I0001,I0002页

作者：蒋大伟樊嘉杰胡栋樊学军张国旗河海大学常州213022 复旦大学工程与应用技术研究院超越照明研究所上海200433 上海市碳化硅半导体功率器件工程技术研究中心上海200433 Department of Microelectronics EEMCS FacultyDelft University of TechnologyDelft 2628the Netherlands Department of Mechanical engineering Lamar UniversityBeaumont TX 77710USA

为了满足第三代半导体低温封装、高温服役的要求,纳米金属颗粒烧结封装互连逐渐替代传统钎料回流焊工艺,而高致密度烧结是实现高可靠性封装的必要条件之一.为了研究纳米铜颗粒烧结互连机理,首先通过非等径双球三维密集堆积模型构建理论... 详细信息

为了满足第三代半导体低温封装、高温服役的要求,纳米金属颗粒烧结封装互连逐渐替代传统钎料回流焊工艺,而高致密度烧结是实现高可靠性封装的必要条件之一.为了研究纳米铜颗粒烧结互连机理,首先通过非等径双球三维密集堆积模型构建理论颗粒配比与堆积孔隙率之间的关系,然后采用蒙特卡罗仿真模拟不同粒径比的双球模型颗粒烧结过程,最后通过纳米铜混合烧结试验来验证理论推算和仿真模拟结果.结果表明,根据3种三维密集堆积模型估算,孔隙率最低时的颗粒粒径比在10∶1~5∶1之间;仿真模拟结果显示,粒径比为5∶1时的双球模型收缩率最大;选择250和50 nm两种粒径纳米铜进行混合烧结试验,证实烧结致密度最佳条件时的颗粒质量比为8∶1,与理论计算结果相符.由此可见,该方法可以为纳米铜烧结在第三代半导体封装互连中的应用和工艺优化提供了理论支持.

关键词：第三代半导体封装互连纳米铜烧结蒙特卡罗仿真模拟致密性

Overview of High Voltage SiC power Semiconductor devices: Development and Application

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CES Transactions on Electrical Machines and Systems 2017年第3期1卷 254-264页

作者： Shiqi Ji Zheyu Zhang Fred(Fei)Wang CURENT&the Department of Electrical engineering and Computer Science University of TennesseeKnoxvilleTN 37996-2250 USA

research on high voltage(HV)silicon carbide(SiC)power semiconductor devices has attracted much attention in recent *** paper overviews the development and status of HV SiC ***,benefits of HV SiC devices are *** technologies and challenges for HV SiC device application in converter design are *** state-of-the-art applications of HV SiC devices are also reviewed.

关键词： High voltage SiC power semiconductor devices SiC-based converter