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A two-dimensional simulation method for investigating charge transport behavior in 3-D charge trapping memory

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Science China Earth Sciences 2016年第12期59卷 188-197页

作者： Zhiyuan LUN Gang DU Kai ZHAO Xiaoyan LIU Yi WANG Institute of Microelectronics Peking University School of Information and Communication Beijing Information Science and Technology University

This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data,which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.

关键词： charge trapping memory semiconductor device modeling 2-D charge transport 3-D NAND flash device modeling and simulation

维普期刊数据库

Estimation of the optical loss in bent-waveguide superluminescent diodes by an analytical method

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Journal of semiconductors 2015年第6期36卷 72-75页

作者：安琪金鹏王占国 China Electronics Standardization Institute Key Laboratory of semiconductor Materials Science and Beijing Key Laboratory of Low-Dimensional semiconductor Mate-rials and devices Institute of semiconductors Chinese Academy of Sciences

The optical loss in the bent region is one of the key features for bent-waveguide superluminescent diodes that affects the device performance greatly under some conditions. For the purpose of device fabrication and optimization, it will be helpful if this bend loss can be estimated. In this letter, we have derived an analytical formula which can be used to get the bend-loss coefficient by fitting the P-I curves of the devices. It is proved that the formula is successful in estimating the loss coefficients from the P-I curves simulated from a complicated quantum-dot device model. We expect this method could also be valid in estimating bend losses of actual devices.

关键词： quantum dots superluminescent diodes semiconductor device modeling

维普期刊数据库

modeling and Measurement of 3D Solenoid Inductor Based on Through-Silicon Vias

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Chinese Journal of Electronics 2023年第2期32卷 365-374页

作者： YIN Xiangkun WANG Fengjuan ZHU Zhangming Vasilis F.Pavlidis LIU Xiaoxian LU Qijun LIU Yang YANG Yintang Shaanxi Key Lab.of Integrated Circuits and Systems School of Microelectronics Xidian University School of Automation and Information Engineering Xi'an University of Technique Department of Computer Science University of Manchester

Through-silicon via(TSV) provides vertical interconnectivity among the stacked dies in three-dimensional integrated circuits(3D ICs) and is a promising option to minimize 3D solenoid inductors for on-chip radio-frequency applications. In this paper, a rigorous analytical inductance model of 3D solenoid inductor is proposed based on the concept of loop and partial inductance. And a series of 3D samples are fabricated on 12-in high-resistivity silicon wafer using low-cost standard CMOS-compatible process. The results of the proposed model match very well with those obtained by simulation and measurement. With this model, the inductance can be estimated accurately and efficiently over a wide range of inductor windings, TSV height, space, and pitch.

关键词： semiconductor device modeling Inductance Analytical models Solid modeling Three-dimensional displays Integrated circuit modeling Inductors

An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

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Chinese Journal of Electronics 2023年第2期32卷 375-388页

作者： CUI Yuqiang SHAN Weiwei DAI Wentao LIU Xinning GUO Jingjing CAO Peng National ASIC System Engineering Research Center Southeast University Cadence Design Systems Inc. Nanjing University of Posts and Telecommunications

In advanced CMOS technology, process,voltage, and temperature(PVT) variations increase the paths’ latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain(FO4 chain) metric has been proven to be a good metric to estimate the path’s delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study,an improved model of path delay variability is established to describe the relationship between the paths’ max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs(i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips’ measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages.

关键词： semiconductor device modeling Monte Carlo methods Temperature Computational modeling Inverters Delays Topology

A Study on Relative Sensitivity of Sector Split-Drain Magnetic Field-Effect Transistor based on Standard CMOS Technology

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A Study on Relative Sensitivity of Sector Split-Drain Magnet...

2006 8th International Conference on Solid-State and Integrated Circuit Technology

作者： ZHU Dazhong LIU Tong GUO Qing Institute of Microelectronics and Optoelectronics Department of Information Science and Electronics Engineering Zhejiang University

ISBN: (纸本)1424401607

＜正＞In this paper,two different methods are used to model the relative sensitivity of sector split-drain magnetic field-effect transistor（MAGFET） based on standard CMOS *** simulation is presented to depict the complicated distribution of electric potential and current in the inversion *** mapping technique is applied to calculate the geometrical correction factor of sector Hall plate,through which the relative sensitivity of sector split-drain magnetic field-effect transistor can be expressed as an analytical model depending on geometric features of the sector *** model developed through numerical simulation and conformal mapping technique is verified by experimental *** research indicates that the theoretical relative sensitivity of the sector split-drain MAGFET is 3.82%/T（3.77%/T is measured in the experiment）,which is higher than the rectangular MAGFET that has been reported.

关键词： CMOS technology Magnetic fields FETs Conformal mapping semiconductor device modeling Numerical simulation Magnetic field measurement Voltage Transistors Analytical models

Advanced Spice modeling for 65nm CMOS Technology

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Advanced Spice Modeling for 65nm CMOS Technology

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Lianfeng Yang Meng Cui James Ma Jia He Wei Wang Waisum Wong ProPlus Design Solutions Inc. semiconductor Manufacturing International Corporation

＜正＞The paper presents a comprehensive study of Spice modeling for some key physical effects observed in a 65nm ***-induced stress effect,well proximity effect,as well as HCI and NBTI reliability effects,which can not be neglected for technologies beyond 90nm and must be properly modeled for accurate circuit simulations,are discussed in this study.

关键词： [IEEE Keyword]Mathematical model semiconductor device modeling Data mining Human computer interaction Stress Integrated circuit modeling Degradation

Non-Contact Inter-Chip Data Communications Technology for System in a Package

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Non-Contact Inter-Chip Data Communications Technology for Sy...

2004 7th International Conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Tadahiro Kuroda Department of Electronics and Electrical Engineering Keio UniversityYokohamaJapan

＜正＞A wireless bus for stacked chips in a package is *** uses inductive coupling of metal inductors on the *** paper discusses inductive inter-chip signaling,transceiver circuit design,modeling of magnetic field and electric circuits,theory for inductor layout optimization,cross talk analysis in its array arrangement,and cross talk countermeasures.A transceiver is designed and fabricated in 0.35μm CMOS and *** maximum data rate is 1.2Gb/s/channel with 45mW from 3.3V in 300μm *** talk is measured by an embedded voltage detector on the *** agreements are found between the measurements and the theoretical *** is found that cross talk is minimized by arranging channels at intervals of a certain distance.A technique based on Time Division Multiple Access is also proposed to further reduce the cross talk.

关键词： Data communication Communications technology Packaging semiconductor device measurement Inductors Transceivers Magnetic field measurement Coupling circuits Circuit synthesis semiconductor device modeling

Optimal Clock Overlapping of Four-phase Dickson Charge Pump for Power Efficiency Improvement

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Optimal Clock Overlapping of Four-phase Dickson Charge Pump ...

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Kai Yu Xuecheng Zou Guoyi Yu Sizhen Li Department of Electronic Science & Technology Huazhong University of Science & Technology

This paper presents a compact power efficiency model to be applied in the analysis and design of clock overlapping of four-phase Dickson charge *** hands in equations on the optimal clock overlapping are concluded Based on 0.25μm CMOS technology,the proposed model is consistent with the simulation result. Both simulation and model validate the optimal clock overlapping range attains better power efficiency when compare conventional designs.

关键词： [IEEE Keyword]Boosting Partial discharges Mathematical model semiconductor device modeling Capacitors Charge pumps Clocks

Investigation of the RESURF Dielectric Inserted （REDI） LDMOS as a novel Silicon-based RF Power device

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Investigation of the RESURF Dielectric Inserted （REDI） LDM...

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Yuchao Liu Han Xiao Ru Huang Institute of Microelectronics Peking University IEEE

＜正＞In this paper,a novel power device named as RESURF Dielectric Inserted（REDI） LDMOS is put *** is fully compatible with standard CMOS technology,which can sharply reduce the *** this novel REDI LDMOS,a RESURF structure and a dielectric region are inserted at the suitable position of the drift region to reconstruct the electric field and the electric potential distributions of the channel region and the drift region,which can effectively reduce the peak electric field and increase the breakdown *** impacts of key device parameters on REDI LDMOS behaviors are comprehensively studied with device simulation *** structural parameters are optimized to obtain acceptable high breakdown voltage（＞10V）,excellent on-state behavior and high frequency performance（＞10GHz）.

关键词： [IEEE Keyword]CMOS integrated circuits Computational modeling semiconductor device modeling Radio frequency Doping Electric fields Dielectrics