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Efficient Statistical leakage power Analysis Method for Function Blocks Considering All Process Variations

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Tsinghua Science and Technology 2007年第S1期12卷 67-72页

作者：骆祖莹 College of Information Science and Technology Beijing Normal University

With technology scaling into nanometer regime, rampant process variations impact visible influences on leakage power estimation of very large scale integrations (VLSIs). In order to deal with the case of large inter- and intra-die variations, we induce a novel theory prototype of the statistical leakage power analysis (SLPA) for function blocks. Because inter-die variations can be pinned down into a small range but the number of gates in function blocks is large(>1000), we continue to simplify the prototype. At last, we induce the efficient methodology of SLPA. The method can save much running time for SLPA in the low power design since it is of the local-updating advantage. A large number of experimental data show that the method only takes feasible running time (0.32 s) to obtain accurate results (3 σ-error leakage power analysis of VLSIs under rampant process variations.

关键词： process variations statistical analysis leakage power very large scale integration (VLSI)

Fast Algorithm for leakage power Reduction by Input Vector Control

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Fast Algorithm for Leakage Power Reduction by Input Vector C...

Dynamic power-gating for leakage power reduction in FPGAs

2005 6th International Conference on ASIC

作者： Xiaotao Chang Dongrui Fan Yinhe Han Zhimin Zhang Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences Graduate School of Chinese Academy of Sciences

ISBN: (纸本)0780392108

＜正＞With leakage power being no longer negligible,it becomes a critical problem for low power *** vector control is an effective method to reduce leakage power when a circuit enters sleep mode. It seeks to find a vector that minimizes leakage power to be statically applied to the primary inputs of a *** this paper,we present a fast algorithm to search the input vector which can lead to the minimal leakage *** order to accelerate the evaluation procedure,the circuit under simulation is reduced by circuit partition based on the level number of circuits ***,a searching algorithm based on sub-circuit is used to find the target input *** results on combinational circuits of ISCAS85 benchmark show this algorithm can accelerate calculation over 5 times.

关键词： leakage power input vector control low power design gate-level simulator

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Frontiers of Information Technology & Electronic Engineering 2023年第4期24卷 582-598页

作者： Hadi JAHANIRAD Department of Electronics and Communication Engineering University of KurdistanSanandaj 66177-15175Iran

Field programmable gate array (FPGA) devices have become widespread in electronic systems due to their low design costs and *** battery-restricted applications such as handheld electronics systems,low-power FPGAs are in great *** power almost equals dynamic power in modern integrated circuit technologies,so the reduction of leakage power leads to significant energy *** propose a power-efficient architecture for static random access memory(SRAM) based FPGAs,in which two modes (active mode and sleep mode) are defined for each *** sleep mode,ultralow leakage power is consumed by the *** module mode changes dynamically from sleep mode to active mode when module outputs evaluate for new input *** producing the correct outputs,the module returns to sleep *** proposed circuit design reduces the leakage power consumption in both active and sleep *** proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementing Microelectronics Center of North Carolina(MCNC) benchmark circuits on FPGA-SPICE *** results show an approximately 95%reduction in leakage power consumption in sleep ***,the total power consumption (leakage+dynamic power consumption) is reduced by more than 15%compared with that of the best previous *** average area overhead (4.26%) is less than those of other powergating designs.

关键词： Field programmable gate array(FPGA) leakage power power-gating Transistor-level circuit design

Key characterization factors of accurate power modeling for Fin FET circuits

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Science China(Information Sciences) 2015年第2期58卷 182-194页

作者： MA KaiSheng CUI XiaoXin LIAO Kai LIAO Nan WU Di YU DunShan Institution of Microelectronics Peking University Department of Computer Science and Engineering The Pennsylvania State UniversityUniversity ParkPA 16801 USA

Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The Fin FET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22 nm technology nodes. However, the power estimation CAD tools for Fin FET are missing at the moment, which mainly results from the absence of Fin FET power analysis and Fin FET power model. Three key factors for Fin FET power model are: the dimension of the look-up-tables, that to find out the most significant factors that influence Fin FET power and to make them as indexes for the look-up-tables; the distance between sampling points; and the interpolation method. In this paper, various factors that may contribute to the Fin FET power consumption are evaluated. Of all the factors, the continuous ones are compared with sensitivity method. As to other discrete factors, methods of building them in power model are given according to the features of the each factor and the way it influences the power. Based on the simulation result, standard cell power library model for Fin FET is proposed. The research work lays foundation for accurate power analysis and modeling for high-level power analysis of Fin FET circuits. Besides, these key factors are also crucial for low-power Fin FET circuit design.

关键词： Fin FET power modeling leakage power internal power input slew output load

leakage-Aware Modulo Scheduling for Embedded VLIW Processors

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Journal of Computer Science & Technology 2011年第3期26卷 405-417页

作者：关永薛京灵 College of Information Engineering Capital Normal University Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word （VLIW） architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based （Directed Acyclic Graph） leakage-aware scheduling algorithm.

关键词： leakage power very long instruction word (VLIW) software pipelining modulo scheduling

leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

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Journal of Computer Science & Technology 2007年第5期22卷 673-680页

作者：王伟胡瑜韩银和李晓维张佑生 School of Computer and Information Hefei University of Technology Hefei 230009China Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080China School of Computer and Information Hefei University of Technology Hefei 230009China

It is a well-known fact that test power consumption may exceed that during functional operation. leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,

关键词： leakage current don't care bits minimum leakage vector leakage power

Low power adiabatic logic based on FinFETs

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Science China(Information Sciences) 2014年第2期57卷 194-206页

作者： LIAO Nan CUI XiaoXin LIAO Kai MA KaiSheng WU Di WEI Wei LI Rui YU DunShan Institute of Microelectronics Peking University

With the aggressive scaling of device technology,the leakage power has become the main part of power consumption,which seriously reduces the energy recovery efciency of adiabatic *** this paper,a novel low-power adiabatic logic based on FinFET devices has been *** to the lower leakage current,higher on-state current and design flexibility of FinFETs,the proposed adiabatic logic shows considerable power reduction,performance improvement and area saving compared with CMOS adiabatic *** 8-state clock chain as the test circuit has been demonstrated based on the 32-nm FinFET Predictive Technology *** simulation results show that adiabatic circuit based on FinFET devices achieves a power reduction of up to84.8%and a limiting frequency of up to 55 GHz.

关键词： leakage power FinFET adiabatic logic power reduction limiting frequency

Fin Field Effect Transistor with Active 4-Bit Arithmetic Operations in 22 nm Technology

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Intelligent Automation & Soft Computing 2023年第2期35卷 1323-1336页

作者： S.Senthilmurugan K.Gunaseelan Department of Electronics and Communication Engineering SRM Valliammai Engineering CollegeChennai603203India Department of Electronics and Communication Engineering College of Engineering GuindyAnna UniversityChennai600025India

A design of a high-speed multi-core processor with compact size is a trending approach in the Integrated Circuits(ICs)fabrication *** whenever device size comes down into narrow,designers facing many power den-sity issues should be reduced by scaling threshold voltage and supply ***,Complementary Metal Oxide Semiconductor(CMOS)technology sup-ports power saving up to 32 nm gate length,but further scaling causes short severe channel effects such as threshold voltage swing,mobility degradation,and more leakage power(less than 32)at gate ***,it directly affects the arithmetic logic unit(ALU),which suffers a signiﬁcant power density of the scaled multi-core ***,it losses reliability features to get overheating and increased *** paper presents a novel power mini-mization technique for active 4-bit ALU operations using Fin Field Effect Tran-sistor(FinFET)at 22 nm *** on this,a diode is directly connected to the load transistor,and it is active only at the saturation region as a ***,the access transistor can cutoff of the leakage current,and sleep transis-tors control theﬂow of leakage current corresponding to each instant ALU *** combination of transistors(access and sleep)reduces the leakage current from micro to ***,the power minimization is achieved by con-necting the number of transistors(6T and 10T)of the FinFET structure to ALU with 22 nm *** simulation concerns,a Tanner(T-Spice)with 22 nm technology implements the proposed design,which reduces threshold vol-tage swing,supply power,leakage current,gate length delay,*** a result,it is quite suitable for the ALU architecture of a high-speed multi-core processor.

关键词： FinFET(22 nm)technology diode connection arithmetic logic unit reduce threshold voltage swing gate length delay leakage power