FELERION: a new approach for leakage power reduction

作     者：Anjana R Ajay Somkuwar 

作者机构：Department of Electronics and CommunicationDr.K.N Modi Universisy Rajasthan India Department of Electronics and CommunicationMANIT Bhopal Madhya Pradesh India 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2014年第35卷第12期

页      面：57-61页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：leakage power sleep transistors FELERION scaling propagation delay power dissipation 

摘      要：The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach.