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design for manufacturability of a VDSM standard cell library

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Journal of Semiconductors 2012年第2期33卷 143-148页

作者： Zhou Chong Chen Lan Zeng Jianping Yin Minghui Zhao Jie College of Physics and Microelectronics Science Hunan UniversityChangsha 410082China Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China

This paper presents a method of designing a 65 nm DFM standard cell *** reducing the amount of the library largely,the process of optical proximity correction（OPC） becomes more efficient and the need for large storage is *** library is more manufacture-friendly as each cell has been optimized according to the DFM rule and optical *** area penalty is minor compared with traditional library,and the timing,as well as power has a good ***,this library has passed the test from the Technology design Department of *** result shows this DFM standard cell library has advantages that improve the yield.

关键词： design for manufacturability reduced standard cell library layout optimization optical simulation yield

Generative Learning in VLSI design for manufacturability: Current Status and Future Directions

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Journal of Microelectronic Manufacturing 2019年第4期2卷 1-12页

作者： Mohamed Baker Alawieh Yibo Lin Wei Ye David Z.Pan Electrical and Computer Engineering University of Texas at AustinAustinUSA78712 School of Electronics Engineering and Computer Science Peking UniversityBeijingChina100871

With the continuous scaling of integrated circuit technologies,design for manufacturability(DFM)is becoming more critical,yet more ***,recent advances in machine learning have provided a new computing paradigm with promising applications in VLSI *** particular,generative learning-regarded among the most interesting ideas in present-day machine learning-has demonstrated impressive capabilities in a wide range of *** paper surveys recent results of using generative learning in VLSI manufacturing modeling and ***,we examine the unique features of generative learning that have been leveraged to improve DFM efficiency in an unprecedented way;hence,paving the way to a new data-driven DFM *** state-of-the-art methods are presented,and challenges/opportunities are discussed.

关键词： design for manufacturability Generative Learning Machine Learning Lithography

可制造性设计(design for manufacturability):Pro/ENGINEER制造软件

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计算机辅助设计与制造 1997年第10期 55-58页

Regular FPGA based on regular fabric

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Journal of Semiconductors 2011年第8期32卷 155-162页

作者：陈迅朱剑文张民选 School of Computer National University of Defense Technology Department of Electrical and Computer Engineering University of TorontoTorontoONM5S3G4Canada

In the sub-wavelength regime,design for manufacturability（DFM） becomes increasingly important for field programmable gate arrays（FPGAs）.In this paper,an automated tile generation flow targeting micro-regular fabric is *** a publicly accessible,well-documented academic FPGA as a case study,we found that compared to the tile generators previously reported,our generated micro-regular tile incurs less than 10%area overhead,which could be potentially recovered by process window optimization,thanks to its superior printability. In addition,we demonstrate that on 45 nm technology,the generated FPGA tile reduces lithography induced process variation by 33%,and reduce probability of failure by 21.2%.If a further overhead of 10%area can be recovered by enhanced resolution,we can achieve the variation reduction of 93.8%and reduce the probability of failure by 16.2%.

关键词： FPGA layout automation design for manufacturability regular design fabric

Structural topology optimization subject to overhang angle constraint with overhang length relaxation in additive manufacturing

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Science China(Technological Sciences) 2022年第6期65卷 1213-1231页

作者： ZHANG KaiQing CHENG GengDong WANG Yu Department of Engineering Mechanics Dalian University of TechnologyDalian 116023China State Key Laboratory of Structural Analysis for Industrial Equipment Dalian University of TechnologyDalian 116023China

This paper studies additive manufacturing(AM) oriented structural topology optimization(TO).The minimum compliance design subject to overhang angle constraint with overhang length relaxation and horizontal minimum length control is *** the overhang length relaxation allows additional flexibility for AM product design,there have been very limited studies on *** paper elucidates that the overhang angle constraint we proposed can identify the lower boundary element that violates the overhang angle *** advantage of this fact,we achieve the overhang length relaxation by specifying that the volume fraction of the elements that violate the overhang angle constraint in each local area of the design domain is less than a specified upper bound.A formula for estimating the maximum allowable overhang length of this method is proposed and *** horizontal minimum length constraint is also employed in this *** controlling the horizontal length size of the structural member,this constraint together with the overhang angle constraint with overhang length relaxation suppresses the hanging *** gradient-based optimization algorithm method of moving asymptotic(MMA) is used to solve the TO *** examples show the effectiveness of this *** is observed that the new constraint alleviates the main issues of traditional overhang angle constraints,i.e.,gray element issue,stress concentration issue,and shattered structure *** with the strict traditional overhang angle constraint,the new formulation reduces structural compliance.

关键词： topology optimization overhang angle constraint overhang length relaxation design for manufacturability additive manufacturing

Full-IC manufacturability check based on dense silicon imaging

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Science in China(Series F) 2005年第4期48卷 533-544页

作者： YANXiaolang SHIZheng CHENYe MAYue GAOGensheng InstituteofVLSIdesign ZhejiangUniversityHangzhou310027China

With the increased design complexities brought in by applying different Reticle Enhancement Technologies (RETs) in nanometer-scale IC manufacturing process, post-RET sign-off verification is quickly becoming necessary. By introducing innovative algorithms for lithographic modeling, silicon imaging and yield problem locating, this paper describes a new methodology of IC manufacturability verification based on Dense Silicon Imaging (DSI). Necessity of imaging based verification is analyzed. Existing post-RET verification methods are reviewed and compared to the new methodology. Due to the greatly improved computational efficiency produced by algorithms such as the ~16*log2N/log2M times faster Specialized FFT, DSI based manufacturability checks on full IC scale, which were impractical for applications before, are now realized. Real verification example has been demonstrated and studied as well.

关键词： RET OPC PSM design for manufacturability photolithography simulation.