检索结果-南通市图书馆

test data compression and test Response Compaction for Broadside Delay testing Using a New Scan Architecture

维普期刊数据库评论

在线全文

维普期刊数据库

学校读者我要写书评

暂无评论

Test Data Compression and Test Response Compaction for Broad...

System-on-Chip test data compression Based on Split-data Variable Length (SDV) Code

第六届中国测试学术会议

作者： Dong Xiang is with the School of Software,Tsinghua University,Beijing 100084,P.R.China Zhen Chen is with Dept.of Comp.Sci.and Technol., Tsinghua University,Beijing 100084,P.R.China.

＜正＞test data compression is a much more difficult problem for broadside delay testing because test data for broadside delay testing is much more than that of stuck-at fault testing, and broadside delay fault test generation in the two-frame circuit model can specify much more inputs.A new scan architecture is proposed to compress test stimulus data,compact test responses and reduce test application time for broadside delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group,where all scan flip-flops in the same group are assigned the same values for all test *** conditions are presented for including any pair of scan flip-flops into the same group for broadside transition,non-robust path delay and robust path delay fault *** data for broadside delay testing based on the new scan architecture can be compressed *** application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for broadside transition,non-robust and robust path delay fault *** scan forest and test response compactor are constructed for further test data *** experimental results are presented to show the effectiveness of the method.

关键词： Broadside delay testing test data compression test response compaction test application cost

来源： cnki会议评论

在线全文

cnki会议

学校读者我要写书评

暂无评论

Circuits and Systems 2016年第8期7卷 1213-1223页

作者： J. Robert Theivadas V. Ranganathan J. Raja Paul Perinbam Department of ECE Research Scholar Anna University Chennai India Department of ECE Vignan University Guntur India Department of ECE KCG College of Technology Chennai India

System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.

关键词： test data compression SDV Codes SOC ATE Benchmark Circuits

ADVANCED FREQUENCY-DIRECTED RUN-LENTH BASED CODING SCHEME ON test data compression FOR SYSTEM-ON-CHIP

维普期刊数据库评论

在线全文

维普期刊数据库

学校读者我要写书评

暂无评论

Transactions of Nanjing University of Aeronautics and Astronautics 2012年第1期29卷 77-83页

作者：张颖吴宁葛芬南京航空航天大学电子信息工程学院

test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes.

关键词： test data compression FDR codes test resource partitioning system-on-chip

An Efficient test data compression Technique Based on Codes

在线全文

学校读者我要写书评

暂无评论

Journal of Semiconductors 2005年第11期26卷 2062-2068页

作者：方建平郝跃刘红侠李康西安电子科技大学微电子学院宽禁带半导体材料与器件教育部重点实验室西安710071

This paper presents a new test data compression/decompression method for SoC testing,called hybrid run length codes. The method makes a full analysis of the factors which influence test parameters：compression ratio,test application time, and area overhead. To improve the compression ratio, the new method is based on variable-to-variable run length codes,and a novel algorithm is proposed to reorder the test vectors and fill the unspecified bits in the pre-processing step. With a novel on-chip decoder, low test application time and low area overhead are obtained by hybrid run length codes. Finally, an experimental comparison on ISCAS 89 benchmark circuits validates the proposed method

关键词： test data compression unspecified bits assignment system-on-a-chip test hybrid run-length codes

Scan Cell Positioning for Boosting the compression of Fan-Out Networks

在线全文

学校读者我要写书评

暂无评论

Journal of Computer Science & Technology 2009年第5期24卷 939-948页

作者： Ozgur Sinanoglu Mohammed Al-Mulla Noora A.Shunaiber Alex Orailoglu Math and Computer Science Department Kuwait University Computer Science and Engineering Department University of CaliforniaSan DiegoLa JollaCA92093 U.S.A.

Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.

关键词： scan-based testing test data compression scan cell reordering scan architecture design

Low Cost Scan test by test Correlation Utilization

在线全文

学校读者我要写书评

暂无评论

Journal of Computer Science & Technology 2007年第5期22卷 681-694页

作者： Ozgur Sinanoglu Mathematics and Computer Science Department Kuwait University SafatKuwait

Scan-based testing methodologies remedy the testability problem of sequential circuits; yet they suffer from prolonged test time and excessive test power due to numerous shift operations. The correlation among test data along with the high density of the unspecified bits in test data enables the utilization of the existing test data in the scan chain for the generation of the subsequent test stimulus, thus reducing both test time and test data volume. We propose a pair of scan approaches in this paper; in the first approach, a test stimulus partially consists of the preceding stimulus, while in the second approach, a test stimulus partially consists of the preceding test response bits. Both proposed scan-based test schemes access only a subset of scan cells for loading the subsequent test stimulus while freezing the remaining scan cells with the preceding test data, thus decreasing scan chain transitions during shift operations. The proposed scan architecture is coupled with test data manipulation techniques which include test stimuli ordering and partitioning algorithms, boosting test time reductions. The experimental results confirm that test time reductions exceeding 97%, and test power reductions exceeding 99% can be achieved by the proposed scan-based testing methodologies on larger ISCAS89 benchmark circuits.

关键词： scan-based testing test data compression test correlation scan architecture design

Enhancing encoding capacity of combinational test stimulus decompressors

在线全文

学校读者我要写书评

暂无评论

Science China(Information Sciences) 2011年第8期54卷 1618-1634页

作者： ALAWADHI Nader SINANOGLU Ozgur AL-MULLA Mohammed Computer Science Department Kuwait University Computer Engineering Department New York University Abu Dhabi

While scan-based compression is widely utilized in order to alleviate the test time and data volume problems,the overall compression level is dictated not only by the chain to channel ratio but also the ratio of encodable *** increasing the number of scan chains in an effort to raise the compression levels may reduce the ratio of encodable patterns,degrading the overall compression *** this paper,we present various methods to improve the ratio of encodable *** methods are based on manipulating the care bit distribution of an unencodable pattern,thereby rendering it compliant with the correlation induced by the decompressor, and thus converting it into an encodable *** proposed transformations,which are simple yet effective,target improvements over fanout and XOR decompressors,while they can be utilized to enhance other types of decompressors, such as multiplexer-based ones;simple nature of these transformations help preserve the simplicity benefits of combinational *** bit manipulation is effected in the form of selective chain delay, selective slice rotate/invert, or both. By developing computationally efficient algorithms and cost-effective hardware blocks for these manipulation methods, we show that the encodability, and thus the compression levels, of stimulus decompressors can be significantly improved through the practical and design flow compatible solution that we propose.

关键词： VLSI test scan-based testing test data compression test pattern encodability add-on blocks

Improved data compression Scheme for Multi-Scan Designs

在线全文

同方期刊数据库

学校读者我要写书评

暂无评论

Tsinghua Science and Technology 2007年第S1期12卷 89-94页

作者：林腾冯建华王阳元 Department of Microelectronics Peking University

This paper presents an improved test data compression scheme based on a combination of test data compatibility and dictionary for multi-scan designs to reduce test data volume and thus test cost. The proposed method includes two steps. First a drive bit matrix with less columns is generated by the compatibilities between the columns of the initial scan bit matrix, also the inverse compatibilities and the logic dependencies between the columns of mid bit matrixes. Secondly a dictionary bit matrix with limited rows is constructed, which has the properties that for each row of the drive bit matrix, a compatible row exists or can be generated by XOR operation of multiple rows in the dictionary bit matrix and the total number of rows used to compute all compatible rows is minimal. The rows in the dictionary matrix are encoded to further reduce the number of ATE channels and test data volume. Experimental results for the large ISCAS 89 benchmarks show that the proposed method significantly reduces test data volume for multi-scan designs.

关键词： test data compression multi-scan design test data volume

A Novel Variable Shifting Code for test compression of SoC

在线全文

学校读者我要写书评

暂无评论

Journal of Electronic Science and Technology of China 2009年第4期7卷 375-379页

作者： Xiao-Le Cui Liang Yin Jin-Xi Hong Ren-Fu Zuo Xiao-Xin Cui Wei Cheng Key Lab of Integrated Microsystems Shenzhen Graduate School of Peking University Shenzhen 518055 China

The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.

关键词： FDR code run-length code test data compression VSPTIDR code.