Scan Cell Positioning for Boosting the Compression of Fan-Out Networks

作     者：Ozgur Sinanoglu Mohammed Al-Mulla Noora A.Shunaiber Alex Orailoglu 

作者机构：Math and Computer Science DepartmentKuwait University Computer Science and Engineering DepartmentUniversity of CaliforniaSan DiegoLa JollaCA92093 U.S.A. 

出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报（英文版）)

年 卷 期：2009年第24卷第5期

页      面：939-948页

核心收录：

学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：scan-based testing test data compression scan cell reordering scan architecture design 

摘      要：Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.