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An 8-bit 100-MS/s pipelined ADC without dedicated sample-and-hold amplifier

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Journal of Semiconductors 2010年第7期31卷 102-107页

作者：张章袁宇丹郭亚炜程旭曾晓洋 State Key Laboratory of ASIC & System Fudan University

An 8-b 100-MS/s pipelined analog-to-digital converter（ADC） is *** the dedicated sample-and -hold amplifier（SHA）,it achieves figure-of-merit and area 21%and 12%less than the conventional ADC with the dedicated SHA,*** closed-loop bandwidth of op amps in multiplying DAC is modeled,providing guidelines for power *** theory is well supported by transistor level simulations.A 0.18-μm 1P6M CMOS process was used to integrate the ADCs,and the measured results show that the effective number of bits is 7.43 bit and 6.94 bit for 1-MHz and 80-MHz input signal,respectively,at 100 MS/*** power dissipation is 23.4 mW including voltage/current reference at 1.8-V supply,and FoM is 0.85 pJ/*** ADC core area is 0.53 mm^*** is -0.99 to 0.76 LSB,and DNL is -0.49 to 0.56 LSB.

关键词： analog-to-digital converter pipelined removing dedicated SHA close-bandwidth figure-of-merit

A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

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Journal of Semiconductors 2011年第4期32卷 145-148页

作者：张小伟胡庆生 Institute of RF- & OE-ICs Southeast University

A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved *** on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μ*** results show that the decoder works well and its speed can be up to 6.25 *** a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.

关键词： SerDes 10 B/8 B decoder pipelined high-speed

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

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Journal of Semiconductors 2010年第9期31卷 134-140页

作者：张章袁宇丹郭亚炜程旭曾晓洋 State Key Laboratory of ASIC & System Fudan University

A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is *** the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage *** results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input *** FoM is 0.33 pJ/*** peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,*** ADC core area is 0.94 mm^2.

关键词： analog-to-digital converter pipelined sampling capacitor two-stage op amp compensation linearity of analog switch sub-1-V bandgap voltage reference

A 1.5 bit/s pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

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Journal of Shanghai Jiaotong university(Science) 2007年第4期12卷 497-500页

作者：李丹戎蒙恬毛军发 School of Electronic Information and Electrical Eng. Shanghai Jiaotong Univ.

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

关键词： charge temporary storage technique (CTST) residual voltage capacitor mismatch pipelined analog-to-digital converter (ADC)

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pipelined多值A/D转换器

电路与系统学报 2001年第2期6卷 83-85页

作者：周选昌浙江大学城市学院信息工程系浙江杭州310015

通过对多值ADC数学表示的分析，指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论，设计了pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。

关键词：多值模数转换器开关信号理论多值逻辑数字电路 pipelined

基于pipelined结构的电流型CMOS模数转换器电路设计

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浙江大学学报（理学版） 2013年第6期40卷 637-640页

作者：周选昌胡晓慧浙江大学城市学院信息与电气工程学院浙江杭州310015

低功耗设计在当前超大规模集成电路中越来越重要.以电流信号为转换对象,利用电流传输理论,结合电流型CMOS电路设计技术,设计了8位基于pipelined结构的ADC电路.结果表明,利用电流型CMOS电路可方便地实现电流信号的加减与放大运算,避免了... 详细信息

低功耗设计在当前超大规模集成电路中越来越重要.以电流信号为转换对象,利用电流传输理论,结合电流型CMOS电路设计技术,设计了8位基于pipelined结构的ADC电路.结果表明,利用电流型CMOS电路可方便地实现电流信号的加减与放大运算,避免了使用传统pipelined电路结构中的运算放大器电路,因此电路结构简单,可显著降低电路的功耗,提高转换速度,计算机仿真结果表明,电路功能正确.

关键词： pipelined 电流型CMOS 模数转换器(ADC)

A 5V 8b 40MSample/s pipelined Analog-to-Digital Converter

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A 5V 8b 40MSample/s Pipelined Analog-to-Digital Converter

1.5位pipelined ADC单级传函的数模分析

2004 7th International Conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Xue Liang Shen Yanzhao Zhang Xiangmin Institute of Microelectronics Tsinghua University Beijing 100084 China

＜正＞In this paper,a 5V 8b 40Msamp les/s pipelined A/D converter is *** A/D converter contains seven stages and each stage realizes a resolution of *** reduce both linear and nonlinear errors,bottom-plate sampling,bootstrap and digital correction techniques are applied in ADC *** clocks are necessary for those *** results are obtained,with 1MHz input signal,the ADC acquired SNDR of 48.2dB,SFDR of 58.2dB and 7.8 *** chip is fabricated in 0.35 m N-well CMOS technology and occupies an area of 4 mm2.

关键词： A/D pipelined Bootstrap Bottom-Plate Sampling

来源： cnki会议评论

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现代电子技术 2012年第4期35卷 195-197页

作者：李博张科峰华中科技大学电子科学与技术系湖北武汉430074

1.5位结构是构成pipelined ADC的基本单元,总结了2位向1.5位方案传函的演变过程,但对转换的最优性并未证明。在此通过理论分析揭示了ADC及其单级传输函数变换的本质,证明了在Pipeline结构中,ADC单级传输函数演变的本质是:通过单级传函... 详细信息

1.5位结构是构成pipelined ADC的基本单元,总结了2位向1.5位方案传函的演变过程,但对转换的最优性并未证明。在此通过理论分析揭示了ADC及其单级传输函数变换的本质,证明了在Pipeline结构中,ADC单级传输函数演变的本质是:通过单级传函的变化,使整个ADC最终的传输函数与我们所习惯使用的(或者说最初使用的),相差不大于1个LSB,同时在参考电压失调,子DAC输出失调或者增益错误方面获得一定的鲁棒性。

关键词： pipelined ADC 1.5位传输函数 DC传输曲线右移Vref/4

Current mode ADC design in a 0.5-μm CMOS process

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Journal of Semiconductors 2009年第6期30卷 88-93页

作者：孙泳来逢昌叶以正 Microelectronics Center Harbin Institute of Technology

This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS *** the global and local bias scheme,the number of interconnect signal lines is reduced numerously,and the ADC exhibits the advantages of scalability and *** using linear capacitance,this ADC can be implemented in a standard digital CMOS process;thus,it is suitable for applications in the system on one chip（SoC） design as an analogue *** show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μ*** the histogram testing method,the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range,*** results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB,DNL/INL are-0.005 to ＋0.027 LSB/-0.1 to ＋0.2 LSB,respectively,under a 5 V supply voltage with a digital error correction technique.

关键词： current mode analog to digital converter pipelined