A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

作     者：张章 袁宇丹 郭亚炜 程旭 曾晓洋 

作者机构：State Key Laboratory of ASIC & SystemFudan University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2010年第31卷第9期

页      面：134-140页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the National High Technology Research and Development Program of China(No.2009AA011600) the Project for Young Scientists Fund of Fudan University,China(No.09FQ33) the State Key Laboratory ASIC & System(Fudan University), China(No.09MS008) 

主　　题：analog-to-digital converter pipelined sampling capacitor two-stage op amp compensation linearity of analog switch sub-1-V bandgap voltage reference 

摘      要：A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is *** the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage *** results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input *** FoM is 0.33 pJ/*** peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,*** ADC core area is 0.94 mm^2.