A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture

作     者：张小伟 胡庆生 

作者机构：Institute of RF- & OE-ICsSoutheast University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2011年第32卷第4期

页      面：145-148页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Project supported by the National High Technology Research and Development Program of China(No2006AA01Z239) 

主　　题：SerDes 10 B/8 B decoder pipelined high-speed 

摘      要：A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved *** on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μ*** results show that the decoder works well and its speed can be up to 6.25 *** a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.