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Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips

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Science China(Information Sciences) 2023年第10期66卷 152-161页

作者： Yuyi LIU Bin GAO Jianshi TANG Huaqiang WU He QIAN School of Integrated Circuits Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua University

computation-in-memory(CIM) chips offer an energy-efficient approach to artificial intelligence computing workloads. Resistive random-access memory(RRAM)-based CIM chips have proven to be a promising solution for overcoming the von Neumann bottleneck. In this paper, we review our recent studies on the architecture-circuit-technology co-optimization of scalable CIM chips and related hardware demonstrations. To further minimize data movements between memory and computing units, architecture optimization methods have been introduced. Then, we propose a device-architecture-algorithm co-design simulator to provide guidelines for designing CIM systems. A physics-based compact RRAM model and an array-level analog computing model were embedded in the simulator. In addition, a CIM compiler was proposed to optimize the on-chip dataflow. Finally, research perspectives are proposed for future development.

关键词： resistive random-access memory computation-in-memory compact model device-architecture-algorithm co-design compiler

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Towards efficient allocation of graph convolutional networks on hybrid computation-in-memory architecture

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Science China(Information Sciences) 2021年第6期64卷 112-125页

作者： Jiaxian CHEN Guanquan LIN Jiexin CHEN Yi WANG College of Computer Science and Software Engineering Shenzhen University

Graph convolutional networks(GCNs) have been applied successfully in social networks and recommendation systems to analyze graph data. Unlike conventional neural networks, GCNs introduce an aggregation phase, which is both computation-and memory-intensive. This phase aggregates features from the neighboring vertices in the graph, which incurs significant amounts of irregular data and memory *** emerging computation-in-memory(CIM) architecture presents a promising solution to alleviate the problem of irregular accesses and provide fast near-data processing for GCN applications by integrating both three-dimensional stacked CIM and general-purpose processing units in the system. This paper presents Graph-CIM, which exploits the hybrid CIM architecture to determine the allocation of GCN ***-CIM models the GCN application process as a directed acyclic graph(DAG) and allocates tasks on the hybrid CIM architecture. It achieves fine-grained graph partitioning to capture the irregular characteristics of the aggregation phase of GCN applications. We use a set of representative GCN models and standard graph datasets to evaluate the effectiveness of Graph-CIM. The experimental results show that Graph-CIM can significantly reduce the processing latency and data-movement overhead compared with the representative schemes.

关键词： computation-in-memory graph convolutional networks hybrid architecture scheduling inference accelerator

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Application of mathematical morphology operation with memristor-based computation-in-memory architecture for detecting manufacturing defects

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Fundamental Research 2022年第1期2卷 123-130页

作者： Ying Zhou Bin Gao Qingtian Zhang Peng Yao Yiwen Geng Xinyi Li Wen Sun Meiran Zhao Yue Xi Jianshi Tang He Qian Huaqiang Wu School of Integrated Circuits(SIC) Beijing Innovation Center for Future Chips(ICFC)Tsingfiua UniversityBeijingChina Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua UniversityBeijingChina

Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image *** data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units(CPUs)and graphics processing units(GPUs).computation-in-memory(CIM)provides a possible solution for highly efficient morphology *** this study,we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromoq)hic computation on a multi-array-based memristor ***-by-pixel logic computations with low parallelism are converted to parallel operations using ***,hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit(IC)manufacturing and medical image *** addition,we developed a new implementation scheme employing a four-layer network to realize small-object detection with high *** system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed,respectively,exhibiting the advantage of the proposed memristor-based morphology operation.

关键词： Memristor computation-in-memory Mathematical morphology Defect detection

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