Architecture-circuit-technology co-optimization for resistive random access memory-based computation-in-memory chips

作     者：Yuyi LIU Bin GAO Jianshi TANG Huaqiang WU He QIAN 

作者机构：School of Integrated Circuits Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua University 

出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期：2023年第66卷第10期

页      面：152-161页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by National Natural Science Foundation of China (Grant Nos. 92064001, 62025111, 92264201) Beijing Advanced Innovation Center for Integrated Circuits 

主　　题：resistive random-access memory computation-in-memory compact model device-architecture-algorithm co-design compiler 

摘      要：Computation-in-memory(CIM) chips offer an energy-efficient approach to artificial intelligence computing workloads. Resistive random-access memory(RRAM)-based CIM chips have proven to be a promising solution for overcoming the von Neumann bottleneck. In this paper, we review our recent studies on the architecture-circuit-technology co-optimization of scalable CIM chips and related hardware demonstrations. To further minimize data movements between memory and computing units, architecture optimization methods have been introduced. Then, we propose a device-architecture-algorithm co-design simulator to provide guidelines for designing CIM systems. A physics-based compact RRAM model and an array-level analog computing model were embedded in the simulator. In addition, a CIM compiler was proposed to optimize the on-chip dataflow. Finally, research perspectives are proposed for future development.