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Simultaneous Accelerator Parallelization and Point-to-Point Interconnect Insertion for Bus-Based Embedded SoCs

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Tsinghua Science and Technology 2015年第6期20卷 644-660页

作者： Daming Zhang Yongpan Liu Shuangchen Li Tongda Wu huazhong yang Department of Electronic Engineering Tsinghua University Department of Electronic and Computer Engineering University of California

As performance requirements for bus-based embedded System-on-Chips(So Cs) increase, more and more on-chip application-specific hardware accelerators(e.g., filters, FFTs, JPEG encoders, GSMs, and AES encoders) are being integrated into their designs. These accelerators require system-level tradeoffs among performance, area, and scalability. Accelerator parallelization and Point-to-Point(P2P) interconnect insertion are two effective system-level adjustments. The former helps to boost the computing performance at the cost of area,while the latter provides higher bandwidth at the cost of routability. What’s more, they interact with each other. This paper proposes a design flow to optimize accelerator parallelization and P2 P interconnect insertion *** explore the huge optimization space, we develop an effective algorithm, whose goal is to reduce total So C latency under the constraints of So C area and total P2 P wire length. Experimental results show that the performance difference between our proposed algorithm and the optimal results is only 2.33% on average, while the running time of the algorithm is less than 17 s.

关键词： accelerator parallelization point-to-point interco

Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection

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Science in China(Series F) 2008年第7期51卷 975-984页

作者： QIAO Fei yang huazhong HUANG Gang WANG Hui NICS Group Department of Electronic Engineering Tsinghua University Beijing 100084 China

A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.

关键词： low power circuit low-swing interface differential signaling tapered-buffer interconnect asynchronous circuit

Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations

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Science in China(Series F) 2007年第4期50卷 587-599页

作者： FAN JianXing yang huazhong WANG Hui YAN XiaoLang HOU ChaoHuan Department of Electronic Engineering Tsinghua University Beijing 100084 China Institute of VLSI Zhejiang University Hangzhou 310027 China Institute of Acoustics Chinese Academy of Sciences Beijing 100080 China

Phase noise analysis of an oscillator is implemented with its periodic time-varying small signal state equations by perturbing the autonomous large signal state equations of the oscillator. In this paper, the time domain steady solutions of oscillators are perturbed with traditional regular method; the periodic time-varying Jocobian modulus matrices are decomposed with Sylvester theorem, and on the resulting space spanned by periodic vectors, the conditions under which the oscillator holds periodic steady states with any perturbations are analyzed. In this paper, stochastic calculus is applied to disclose the generation process of phase noise and calculate the phase jitter of the oscillator by injecting a pseudo sinusoidal signal in frequency domain, representing the white noise, and a δcorrelation signal in time domain into the oscillator. Applying the principle of frequency modulation, we learned how the power-law and the Lorentzian spectrums are formed. Their relations and the Lorentzian spectrums of harmonics are also worked out. Based on the periodic Jacobian modulus matrix, the simple algorithms for Floquet exponents and phase noise are constructed, as well as a simple case is demonstrated. The analysis difficulties and the future directions for the phase noise of oscillators are also pointed out at the end.

关键词： phase noise periodic time-varying Sylvester theorem power-law spectrum Lorentzian spectrum Floquet exponent stochastic calculus

AN ACCURATE PREDICTION MODEL FOR COMPUTATIONAL OVERHEADS OF SECURITY MECHANISMS IN WIRELESS SENSOR NETWORKS

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Journal of Electronics(China) 2009年第5期26卷 699-705页

作者： Liu Wei Luo Rong yang huazhong Department of Electronic Engineering Tsinghua University Beijing 100084 China

In Wireless Sensor Networks (WSNs), it is necessary to predict computational overheads of security mechanisms without final implementations to provide guidelines for system design. This paper presents an accurate and flexible model to predict overheads of these mechanisms. This model is based on overheads of basic operations frequently used in cryptography algorithms, which are essential elements of security mechanisms. Several popular cryptography algorithms and security mechanisms are evaluated using this model. According to simulation results, relative prediction errors are less than 7% for most cryptography algorithms and security mechanisms.

关键词： Wireless Sensor Network (WSN) Cryptography algorithm Security mechanism Computational overhead

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

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Journal of Electronics(China) 2007年第3期24卷 374-379页

作者： Mao Xiaojian yang huazhong Wang Hui Department of Electronic Engineering Tsinghua University Beijing 100084 China

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.

关键词： Fractional-N Frequency synthesizer Phase Locked Loop (PLL) Sigma-Delta Modulator(SDM)

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电缆中间接头缺陷仿真与局部放电实验研究

河南工学院学报 2024年第2期32卷 1-7页

作者：赵筱赫杨捷李士强史炳杰龙金易杨化忠河南工学院电气工程与自动化学院河南新乡453003 河南省线缆结构与材料重点实验室河南新乡453003 韩国东西大学研究生院韩国釜山47011 河南省新能源发电关键装备工程研究中心河南新乡453003 中国科学院电工研究所北京100190 沈阳工业大学辽宁沈阳110000

由于电缆接头制作工艺的影响,中低压电缆的中间接头故障率较高。以10 kV XLPE电缆为对象,研究缺陷类型对电缆局部电场分布与局部放电特性的影响。通过构建电场分析的仿真模型,搭建局部放电实验平台,研究不同的电缆接头制作缺陷对电缆接... 详细信息

由于电缆接头制作工艺的影响,中低压电缆的中间接头故障率较高。以10 kV XLPE电缆为对象,研究缺陷类型对电缆局部电场分布与局部放电特性的影响。通过构建电场分析的仿真模型,搭建局部放电实验平台,研究不同的电缆接头制作缺陷对电缆接头局部电场畸变的影响,对实验试样进行局部放电实验。结果表明,电缆接头制作过程中不同类型的缺陷及缺陷大小对电缆接头部位电场分布、电场的畸变程度、放电初始电压与放电量均有不同程度的影响。研究结果为构建电缆线路工作状态在线监测系统以及电缆运行状态评估与故障诊断提供了依据。

关键词：电缆中间接头工艺缺陷电场分布局部放电

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication

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Journal of Computer Science & Technology 2016年第1期31卷 3-19页

作者： Lixue Xia Peng Gu Boxun Li Tianqi Tang Xiling Yin Wenqin Huangfu Shimeng Yu Yu Cao Yu Wang huazhong yang Department of Electronic Engineering Tsinghua University Beijing 100084 China Tsinghua National Laboratory for Information Science and Technology (TNList) Tsinghua University Beijing 100084 China School of Electrical Computer and Energy Engineering Arizona State University Arizona 85281 U.S.A.

Matrix-vector multiplication is the key operation for many computationally intensive algorithms. The emerging metal oxide resistive switching random access memory （RRAM） device and RRAM crossbar array have demonstrated a promising hardware realization of the analog matrix-vector multiplication with ultra-high energy efficiency. In this paper, we analyze the impact of both device level and circuit level non-ideal factors, including the nonlinear current-voltage relationship of RRAM devices, the variation of device fabrication and write operation, and the interconnect resistance as well as other crossbar array parameters. On top of that, we propose a technological exploration flow for device parameter configuration to overcome the impact of non-ideal factors and achieve a better trade-off among performance, energy, and reliability for each specific application. Our simulation results of a support vector machine （SVM） and Mixed National Institute of Standards and Technology （MNIST） pattern recognition dataset show that RRAM crossbar array based SVM is robust to input signal fluctuation but sensitive to tunneling gap deviation. A further resistance resolution test presents that a 6-bit RRAM device is able to realize a recognition accuracy around 90%, indicating the physical feasibility of RRAM crossbar array based SVM. In addition, the proposed technological exploration flow is able to achieve 10.98% improvement of recognition accuracy on the MNIST dataset and 26.4% energy savings compared with previous work. Experimental results also show that more than 84.4% power saving can be achieved at the cost of little accuracy reduction.

关键词： resistive switching random access memory (RRAM) machine learning electronic design automation matrixvector multiplication non-ideal factor

Nano-flower spherical SnS2 combined with a special lithium storage mechanism as a multifunctional separator for lithium-sulfur batteries contributes to ultra-high initial discharge specific capacity

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Science China(Technological Sciences) 2024年第2期67卷 509-519页

作者： LIU huazhong XIONG YaPing HUANG MouZhi CHEN ZongMin yang Xiao ZHANG Ze yang ZhenYu CAI JianXin School of Chemistry&Chemical Engineering Nanchang UniversityNanchang 330031China

The critical factors that limit the electrochemical performance of lithium-sulfur(Li-S)batteries are mainly the“shuttle effect”of polysulfides and the slow redox reaction between lithium polysulfides(LiPSs).Herein,a nano-sphere-type material selfassembled from tin disulfide nanosheets is designed and applied to the Li-S cell separator in this *** SnS_(2)@PP modified separator not only acts as a dual restriction for LiPSs by chemisorption and physical *** the same time,it improves the catalytic activity of the redox reaction between *** SnS_(2)has extremely high electrochemical ***,a portion of the lithium ions can be inserted into SnS_(2)to form Li_(x)SnS_(2)and contribute to the capacity during the first discharge of the *** addition,Li_(x)SnS_(2)possesses a high degree of stability,and it does not undergo further de-alloying reactions even at the high potential of the Li-S *** benefit is that the steady-state Li_(x)SnS_(2)acts as a lithium-containing *** can form special Li^(+)channels on the surface of the separator,thus greatly improving the efficiency of Li+*** results showed that the SnS_(2)@PP-based cell exhibited extremely high initial discharge specific capacity(1477 m Ah g^(-1)at 0.1 C)and excellent rate performance(631 m Ah g^(-1)at 5 C).Even after 1000 cycles at 2 C,the cell exhibited a low decay rate of 0.06%per cycle on *** addition,the superior electrochemical performance was obtained even with a high sulfur loading of 5.1 mg cm^(-2)and low electrolyte of E/S=8μL mg^(-1).

关键词： Li-S batteries modified separators polysulfides catalytic conversion high electrochemical activity

A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP

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Journal of Electronics(China) 2011年第3期28卷 402-408页

作者： Yu Guangming Wang Yu yang huazhong Department of Electronic Engineering Tsinghua National Laboratory for Information Science and Technology （ TNList） Tsinghua University Beijing 100084 China

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

关键词： Low power Power management All-Digital Phase-Locked Loop (ADPLL) Time-to-Digital Converter (TDC)