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Cir.uits and Systems 2016年第10期7卷 3310-3319页

作者： M. S. Sar.vanan r. jeyabharath Depar.ment of ECE Mahendra College of Engineering Salem India Depar.ment of EEE KSR Institute for Engineering and Technology Tiruchengode India

This wor. pr.sents an implementation of an innovative single phase multilevel inver.er.using capacitor. with r.duced switches. The pr.posed Capacitor.patter. H-br.dge Multilevel Inver.er.(CPHMLI) topology consists of a pr.per.number.of Capacitor.connected with switches and power.sour.es. The advanced switching contr.l supplied by Pulse Width Modulation (PDPWM) to attain mixed stair.ase switching state. The char.ing and dischar.ing mode ar. achieved by calculating the voltage er.or.at the load. Fur.her.or., to accomplish the higher.voltage levels at the output with less number.of semiconductor. switches and simple commutation designed using CPHMLI topology. To pr.ve the per.or.ance and effectiveness of the pr.posed appr.ach, a set of exper.ments per.or.ed under.var.ous load conditions using MATLAB tool.

关键词： Switched Capacitor.Multilevel Inver.er Phase Diposition Pulse Width Modulation Capacitor.Patter. Based Multilevel Inver.er Total Har.onic Distor.ion Cascaded H-Br.dge 17-Level Inver.er

r.de thr.ugh Str.tegy for.a Thr.e-Level Dual Z-Sour.e Inver.er.Using Tr.AC

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Cir.uits and Systems 2016年第11期7卷 3911-3921页

作者： A. Nazar.Ali Dr. r. jeyabharath K. r.makr.shnan College of Technology Trichy Tamilnadu India K.S.r.Institute for.Engineer.ng and Technology Namakkal Tamilnadu India

A new r.de thr.ugh str.tegy is intr.duced in a thr.e-level dual Z-sour.e inver.er. for.isolation under.semiconductor.switching failur. condition. Her. the output will have no significant decr.ase in the amplitude and quality. Instead of diodes, the tr.acs ar. added to the inver.er.sour.e ends, as it can per.or. a bidir.ctional power.tr.nsfer.also it can oper.te well in both low and high voltage oper.ting conditions. The faulted par. can be isolated by simply alter.ng the fir.ng pulses for.tur.ing on/off the tr.acs using the car.ier.based SPWM technique and r.sulting in a boosting output with zer. common mode voltage. Consequently, it for.s a common floating point or.null point with a zer. common mode voltage. It is exper.mentally ver.fied by using MATLAB, and digital oscilloscope.

关键词： Common Mode Voltage Fault Compensation Thr.e-Level Inver.er Sinusoidal Pulse Width Modulation Z-Sour.e Inver.er

FPGA SoC Based Multichannel Data Acquisition System with Networ. Contr.l Module

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Cir.uits and Systems 2017年第2期8卷 53-75页

作者： C. r.jasekar.n r. jeyabharath P. Veena Depar.ment of ECE K S Rangasamy College of Technology Tiruchengode India Depar.ment of EEE K S R Institute for Engineering and Technology Tiruchengode India

Nor.ally, Data acquisition (DAQ) is used to acquir. the signals fr.m differ.nt devices like sensor., tr.nsducer., actuator. etc. The data acquisition is also used to analyze the signals, digitizing the signals and acquir.ng the signals fr.m differ.nt inputs. The main dr.wbacks in data acquisition system ar. data stor.ge, har.war. size and r.mote monitor.ng. The System-on-Chip Field Pr.gr.mmable Gate Ar.ay (SoC-FPGA) is used in the pr.posed system in the aim to r.duce the har.war. and memor. size. Fur.her.to pr.vide r.mote monitor.ng with Ether.et/Wi-Fi, the Networ. Contr.l Module (NCM) is integr.ted with Data acquisition and pr.cessing module for.the communication between the systems. This developed system achieves high r.solution with memor. r.duction, r.duced har.war. size, fast r.mote monitor.ng and contr.l. It is used for.r.al time pr.cessing in DAQ and signal pr.cessing. For.fault toler.nce and por.ability, the full system r.configur.bility based FPGA acts as the best solution and the system can be r.used with differ.nt configur.tions. The contr.l of data acquisition and the subsequent management of data ar. coded in LabVIEW. LabVIEW tool is used to design and develop a four.channel Data Acquisition and Pr.cessing (DAQP) unit. National Instr.ments Data Acquisition (NIDAQ) and National Instr.ments Field Pr.gr.mmable Gate Ar.ay (NIFPGA) ar. used to test and implement the design for.r.al time pr.cessing. This is designed to pr.vide high accur.cy, stor.ge and por.ability.

关键词： DAQ r.al Time Monitor.ng SoC FPGA Multichannel & Data Stor.ge

Har.onic Minimization in Seven Level Cascaded Multilevel Inver.er.Using Selective Har.onic Elimination PWM Techniques

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Cir.uits and Systems 2016年第14期7卷 4322-4330页

作者： V. r. Velmur.gan jeyabharath r.jaiah Veena Par.sunath Depar.ment of EEE PAC Ramasamy Raja Polytechnic College Rajapalayam India Depar.ment of EEE KSR Institute for Engineering and Technology Namakkal India

This paper.concentr.tes on enhancing the pr.ductivity of the multilevel inver.er.and natur. of yield voltage wavefor.. Seven level lessened switches topology has been actualized with just seven switches. Essential Switching plan and Selective Har.onics Elimination wer. executed to diminish the Total Har.onics Distor.ion (THD) esteem. Selective Har.onics Elimination Stepped Wavefor. (SHESW) str.tegy is executed to dispense with the lower.or.er.har.onics. Fundamental switching plan is utilized to contr.l the switches in the inver.er. The pr.posed topology is r.asonable for.any number.of levels. The har.onic lessening is accomplished by selecting fitting switching angles. It indicates would like to decr.ase star.ing expense and unpr.dictability consequently it is able for.moder. applications. In this paper. thir. and fifth level har.onics have been disposed of. Simulation wor. is done utilizing the MATLAB/Simulink pr.gr.mming r.sults have been displayed to accept the hypothesis.

关键词： Multilevel Inver.er PSIM Fundamental Switching Scheme Selective Har.onics Elimination

An Optimal Contr.l Theor. Based Analysis of Br.shless DC Motor.Dr.ve

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Cir.uits and Systems 2016年第10期7卷 3384-3391页

作者： Mur.gan Mar.muthu jeyabharath r.jaiah K. S. r.ngasamy College of Technology Tiruchengode India K. S. r. Institue for.Engineer.ng and Technology Tiruchengode India

The application of BLDC motor.dr.ves in industr.es is becoming mor. popular.nowadays. An er.or.will occur.in the dr.ve that is or.ginated by some distur.ances which ar. the major.pr.blems to r.duce the stability of the system. To obtain the minimum per.or.ance index, the optimal contr.l signal is for.ulated, which is the main objective of this paper. Based on quadr.tic per.or.ance index, the optimal contr.l system of BLDC motor.dr.ve is a design which spotlights in this paper. The complexity of the mathematical expr.ssions has been r.duced by using state space appr.ach to the BLDC system. The bur.en to the contr.l engineer. has r.duced based on tedious computation by using thus optimal design. To pr.vide the desir.d oper.ting per.or.ance, this optimal design helps to r.alize the BLDC system with pr.ctical components.

关键词： BLDC Motor Optimal Contr.l Per.or.ance Index Stability Analysis and State Var.ables

Har.onic Minimization in Seven-Level Cascaded Multilevel Inver.er.Using Evolutionar. Algor.thm

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Cir.uits and Systems 2016年第9期7卷 2309-2322页

作者： jeyabharath r.jaiah Velmur.gan r.mar.Veena Par.sunath Depar.ment of EEE KSR Institute for Engineering and Technology Tamilnadu India Depar.ment of EEE PAC Ramasamy Raja Polytechnic College Tamilnadu India

Inver.er. ar. power.electr.nic devices that change over.DC to sinusoidal AC quantity. Be that as it may, in down to ear.h, these devices pr.duce non-sinusoidal yield which contains har.onics, so as to blend a close sinusoidal component and to lessen the har.onic distor.ion multilevel inver.er. developed. Mathematical methods, which wer. developed, ar. der.vative based and need initial consider.tions. To over.ome this, evolutionar. algor.thms, which ar. der.vative fr.e and accur.te, wer. developed for.obtaining multi levels of output voltage. The pr.posed wor. uses two evolutionar. algor.thms, namely, Genetic Algor.thm (GA) and Par.icle Swar. Optimization (PSO) algor.thm. These algor.thms ar. used to gener.te the switching angles by satisfying the non linear.tr.nscendental equations that gover. the low or.er.har.onic components. A seven level cascaded full br.dge inver.er.is designed using MATLAB/Simulink and the r.sults validate the r.sults for.switching angles. The Total Har.onic Distor.ion (THD) value obtained for.GA and PSO is 11.81% and 10.84% r.spectively. The solution obtained fr.m GA algor.thm was implemented in har.war. using dsPIC contr.ller.to validate the simulation r.sults. The THD value obtained for.cascaded seven-level multilevel inver.er.in the har.war. pr.totype is 25.9%.

关键词： Multilevel Inver.er Selective Har.onic Elimination Genetic Algor.thm Par.icle Swar. Optimization Har.onic Minimization

Analysis and Design of Single Switch Hybr.d Step-Up Conver.er

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Cir.uits and Systems 2016年第4期7卷 211-221页

作者： r.vivar.an Shanmugasundar.m jeyabharath r.jaiah Veena Par.sunath Depar.ment of EEE K. S. Rangasamy College of Technology Tamilnadu India Depar.ment of EEE KSR Institute for Engineering and Technology Tamilnadu India

A Single Switch Hybr.d Step-up Conver.er.with high voltage gain, which is suitable for.r.newable ener.y system, is pr.posed in this paper. The pr.posed conver.er.consists of one switched diode-inductor.cell and a capacitor. While switching, both ar. char.ed in par.llel fr.m the input sour.e and dischar.ed in ser.es to the output. In or.er.to obtain extr. voltage gain at lower.duty cycle, the voltage multiplier.cell is integr.ted with the pr.posed conver.er. The main advantages of the conver.er.ar. high voltage gain, r.duced voltage str.ss, simple str.ctur. and low output voltage r.pples. The oper.ting pr.nciple and steady state theor.tical analysis ar. pr.sented. A 250 W pr.totype conver.er.is implemented with 12 V input and 120 V output to ver.fy the design and analysis of this conver.er.and it has an efficiency of over.90% in all oper.tions.

关键词： DC-DC Power.Conver.ion Switched-Inductor Step-Up Conver.er Voltage Multiplier

New DCM Oper.ted Single Phase Br.dgeless Cuk Der.ved Conver.er. for.Power.Factor.Cor.ection

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Cir.uits and Systems 2016年第9期7卷 2176-2188页

作者： P. M. Dhanasekar.n Par.sunath Veena r.jaiah jeyabharath Depar.ment of EEE K. S. Rangasamy College of Technology Thiruchengode Tamil Nadu India Depar.ment of EEE KSR Institute for Engineering and Technology Thiruchengode Tamil Nadu India

This paper.pr.sents a power.factor.cor.ected (PFC) new br.dgeless (BL) Cuk Topologies for.low power.applications. A BL configur.tion of Cuk conver.er.is pr.posed which eliminates the usage of diode br.dge r.ctifier.at the fr.nt end of the PFC conver.er. thus r.ducing the switching and conduction losses coupled with it. This new BL Cuk conver.er.has two semiconductor. switches. The cur.ent flow dur.ng each switching cycle inter.al of the conver.er.r.duces the conduction losses compar.d to the conventional Cuk PFC conver.er. It also r.duces the input cur.ent r.pple and Electr.magnetic Inter.er.nce (EMI). The inr.sh cur.ent dur.ng the star.ing per.od is limited and the input, output cur.ents of the conver.er.ar. continuous with minimum cur.ent r.pple. Hence it is pr.fer.ed mostly compar.d to other.PFC cir.uits. The pr.posed topology wor.s in the Discontinuous Conduction Mode (DCM) with simple contr.l cir.uitr. to achieve almost a unity power.factor.with less distor.ion in the input AC cur.ent. The switching of the power.switches is done under.zer. cur.ent. The pr.posed PFC topologies ar. theor.tically investigated and per.or.ance compar.sons ar. made with the conventional r.ctifier.. The pr.posed PFC conver.er.is simulated in MATLAB/SIMULINK with Fuzzy Logic Contr.ller.(FLC) and r.sults ar. demonstr.ted to evaluate the effectiveness of the contr.ller.

关键词： Br.dgeless (BL) Cuk Conver.er.Topology Power.Factor.Cor.ection (PFC) Total Har.onic Distor.ion (THD) Fuzzy Logic Contr.ller.(FLC)