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Design of 512-bit logic process-based single poly EEPROM IP

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Journal of Central South University 2011年第6期18卷 2036-2044页

作者：金丽妍 JANG Ji-Hye 余忆宁 HA Pan-Bong kim young-hee Department of Electronic Engineering Changwon National University

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.

关键词： single poly EEPROM cell Fowler-Nordheim tunneling logic process radio frequency identification small area

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

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Journal of Central South University 2012年第1期19卷 168-173页

作者： JANG Ji-Hye 金丽妍 JEON Hwang-Gon kim Kwang-Il HA Pan-Bong kim young-hee Department of Electronic Engineering Changwon National University9 Sarim-DongChangwon 641-773Korea

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

关键词： eFuse differential paired efuse cell one time programmable memory sensing resistance D flip-flop based sense amplifier

Design of 256 bit single-poly MTP memory based on BCD process

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Journal of Central South University 2012年第12期19卷 3460-3467页

作者： kim Kwang-il kim Min-sung PARK young-bae PARK Mu-hun HA Pan-bong kim young-hee Department of Electronic Engineering Changwon National University9 Sarim-DongChangwon 641-773Korea

We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.

关键词： multi-time programmable memory PMIC cross-coupled charge pump

Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

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Journal of Central South University 2012年第2期19卷 417-423页

作者： LEE Jae-hyung 金丽妍余忆宁 JANG Ji-hye kim Kwang-il HA Pan-bong kim young-hee Department of Electronic Engineering Changwon National University9 Sarim-Dong

The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.

关键词： 1 T-static random access memory direct current-direct current converter positive word-line voltage negative word-line voltage half- VDb generator

Design of 32 kbit one-time programmable memory for microcontroller units

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Journal of Central South University 2012年第12期19卷 3475-3483页

作者： JEON Hwang-gon CHOI In-hwa HA Pan-bong kim young-hee Department of Electronic Engineering Changwon National University9 Sarim-DongChangwon 641-773Korea

A 32 kbit OTP(one-time programmable)memory for MCUs(micro-controller units)used in remote controllers was *** OTP memory is used for program and data *** is required to apply 5.5V to BL(bit-line)and 11V to WL(word-line)for a OTP cell of 0.35μm ETOX(EEPROM tunnel oxide)type by *** use 5V transistors on column data paths to reduce the area of column data paths since they require small *** addition,we secure device reliability by using HV(high-voltage)transistors in the WL ***,we change from a static logic to a dynamic logic used for the WL driver in the core ***,we optimize the WD(write data)switch ***,we can implement them with a small-area *** addition,we implement the address predecoder with a small-area logic *** area of the designed 32 kbit OTP with 5V and HV devices is 674.725μm×258.75μm(=0.1745mm2)and is 56.3% smaller than that using 3.3V devices.

关键词： one-time programmable memory micro controller unit EEPROM tunnel oxide small-area

Design of 32-bit differential paired eFuse OTP memory in a form of two-dimensional array

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Journal of Central South University 2012年第12期19卷 3484-3491页

作者： kim Yoon-kyu JANG Ji-hye YOON Geon-soo LEE Dong-hoon HA Man-yeong HA Pan-bong kim young-hee Department of Electronic Engineering Changwon National University9 Sarim-DongChangwon 641-773Korea

A differential paired eFuse OTP(one-time programmable)memory cell which can be configured into a 2D(two-dimensional)eFuse cell array was *** sensible resistance of a programmed eFuse link is a half smaller than that of the single-ended counterpart and BL datum can be sensed without a reference *** this 2D array of differential paired eFuse OTP memory cells,we design a 32-bit eFuse OTP memory *** use a sense amplifier based D F/F circuit as the BL(bit-line)SA(sense amplifier)and design a sensing margin test circuit with a variable pull-up *** is confirmed by the function test that the designed 32-bit OTP memory IP functions normally on 30 sample dies.

关键词： eFuse one-time programmable memory 2-dimensional array

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常山根水提物在大鼠肝脏中的抗炎作用

Acta Pharmacologica Sinica 2003年第2期24卷 127-132页

作者： CHOI Byung-Tae LEE Jun-Hyuk KO Woo-Shin kim young-hee CHOI Yung-Hyun KANG Ho-Sung kim Han-Do Department of Anatomy College of Oriental Medicaine dongEui Universtity Busan 614-052 Kore. Department of Oriental Medicine College of Oriental Medicine Research Institute of Oriental Medicine Dong-Eui University Busan 614-052 Department of Oriental Medicine College of Oriental Medicine Research Institute of Oriental Medicine Dong-Eui University Busan 614-052 Department of Molecular Biology College of Natural Sciences Pusan National University Busan 609-735 Korea Department of Molecular Biology College of Natural Sciences Pusan National University Busan 609-735 Korea Department of Molecular Biology College of Natural Sciences Pusan National University Busan 609-735 Korea Department of Molecular Biology College of Natural Sciences Pusan National University Busan 609-735 Korea

AIM: To study the anti-inflammatory effects of aqueous extract from Dichroafebrifuga root (AEDF) for suppression in the process of lipopolysaccharide (LPS)-induced sepsis in the rat liver. METHODS: The inhibitory effect of AEDF on the alteration of inflammatory proteins was investigated by Western blot and immunohistochemical analysis. RESULTS: Western blot analysis showed that the level of nuclear factor (NF)-κBp65 was markedly up-regulated and (Ⅰ)κBα was down-regulated by LPS (8 mg/kg) challenge. However, AEDF 100 mg/kg inhibited induction of NF-κBp65 and degradation of Ⅰ-κBα in the liver of LPS-challenged rats. Immunohistochemical analysis showed that while the expression of the NF-κBp65, tumor necrosis factor (TNF)-α, and inducible nitric oxide synthase(iNOS) tended to increase, that of Ⅰ-κBα was decreased in the hepatocytes of rats challenged with LPS. A slight decline of NF-κBp65, TNF-α, and iNOS, but an increase of Ⅰ-κBα were observed in the hepatocytes of the rats pretreated with AEDF. CONCLUSION: AEDF may act as a therapeutic agent for inflammatory disease through a regulation of inflammation-related proteins.

关键词：常山炎症脂多糖类核因子-кB IкB 肿瘤坏死因子一氧化氮合酶

车用仪表背光灯的LED线性恒流驱动电路设计

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微电子学 2011年第1期41卷 82-85页

作者：李龙镇任正权 HA Pan-Bong kim young-hee 延边大学工学院计算机科学系韩国昌原大学电子工程系

阐述了可用于车用仪表背光灯的高精度LED线性恒流驱动芯片设计,重点讨论在设计并联方式LED线性恒流驱动电路时如何消除连线分布电阻的影响,并推出一种新颖的可消除连线分布电阻影响的电路,最终通过电路模拟测试加以验证。研究结果表明,... 详细信息

阐述了可用于车用仪表背光灯的高精度LED线性恒流驱动芯片设计,重点讨论在设计并联方式LED线性恒流驱动电路时如何消除连线分布电阻的影响,并推出一种新颖的可消除连线分布电阻影响的电路,最终通过电路模拟测试加以验证。研究结果表明,在设计高精度、高稳定性、大电流、并联方式LED线性恒流驱动电路时,消除连线分布电阻影响很有必要。

关键词： LED 线性恒流驱动电路分布电阻

A New Encryption Mechanism Supporting the Update of Encrypted Data for Secure and Efficient Collaboration in the Cloud Environment

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Computer Modeling in Engineering & Sciences 2025年第1期142卷 813-834页

作者： Chanhyeong Cho Byeori kim Haehyun Cho Taek-young Youn Department of Cyber Security Dankook UniversityYongin16890Republic of Korea Department of Software Soongsil UniversitySeoul07027Republic of Korea

With the rise of remote collaboration,the demand for advanced storage and collaboration tools has rapidly ***,traditional collaboration tools primarily rely on access control,leaving data stored on cloud servers vulnerable due to insufficient *** paper introduces a novel mechanism that encrypts data in‘bundle’units,designed to meet the dual requirements of efficiency and security for frequently updated collaborative *** bundle includes updated information,allowing only the updated portions to be reencrypted when changes *** encryption method proposed in this paper addresses the inefficiencies of traditional encryption modes,such as Cipher Block Chaining(CBC)and Counter(CTR),which require decrypting and re-encrypting the entire dataset whenever updates *** proposed method leverages update-specific information embedded within data bundles and metadata that maps the relationship between these bundles and the plaintext *** utilizing this information,the method accurately identifies the modified portions and applies algorithms to selectively re-encrypt only those *** approach significantly enhances the efficiency of data updates while maintaining high performance,particularly in large-scale data *** validate this approach,we conducted experiments measuring execution time as both the size of the modified data and the total dataset size *** show that the proposed method significantly outperforms CBC and CTR modes in execution speed,with greater performance gains as data size ***,our security evaluation confirms that this method provides robust protection against both passive and active attacks.

关键词： Cloud collaboration mode of operation data update efficiency