Design of 512-bit logic process-based single poly EEPROM IP

作     者：金丽妍 JANG Ji-Hye 余忆宁 HA Pan-Bong KIM Young-Hee 

作者机构：Department of Electronic Engineering Changwon National University 

出 版 物：《Journal of Central South University》 (中南大学学报（英文版）)

年 卷 期：2011年第18卷第6期

页      面：2036-2044页

核心收录：

学科分类：1305[艺术学-设计学（可授艺术学、工学学位）] 080903[工学-微电子学与固体电子学] 13[艺术学] 0809[工学-电子科学与技术（可授工学、理学学位）] 081104[工学-模式识别与智能系统] 08[工学] 0804[工学-仪器科学与技术] 081101[工学-控制理论与控制工程] 0811[工学-控制科学与工程] 

基　　金：Project(10039239) supported by the Industrial Strategic Technology Development Program Funded by the Ministry of Knowledge Economy  Korea 

主　　题：single poly EEPROM cell Fowler-Nordheim tunneling logic process radio frequency identification small area 

摘      要：A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.