Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

作     者：JANG Ji-Hye 金丽妍 JEON Hwang-Gon KIM Kwang-Il HA Pan-Bong KIM Young-Hee 

作者机构：Department of Electronic EngineeringChangwon National University9 Sarim-DongChangwon 641-773Korea 

出 版 物：《Journal of Central South University》 (中南大学学报（英文版）)

年 卷 期：2012年第19卷第1期

页      面：168-173页

核心收录：

学科分类：080202[工学-机械电子工程] 08[工学] 0802[工学-机械工程] 

基　　金：Electronics and Telecommunications Research Institute  ETRI 

主　　题：eFuse differential paired efuse cell one time programmable memory sensing resistance D flip-flop based sense amplifier 

摘      要：For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.