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Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection

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Science china(Information Sciences) 2019年第6期62卷 79-86页

作者： Lizhong zhang Yuan wang Yize wang {3. zhang yandong he Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of MicroelectronicsPeking University

A conventional diode-triggered silicon-controlled rectifier(DTSCR) structure with a layout strategy for electrostatic discharge(ESD) protection is presented and confirmed in a 65-nm CMOS *** modified device is featured by a scaled-down trigger-diode string, which shortens its turn-on time using a variable scaling factor. To confirm the parasitic resistance adjustments of the modified DTSCR, transmission line pulsing(TLP)/very fast transmission line pulsing(VF-TLP) tests and simulations are performed on the device. Compared to a conventional DTSCR, this structure exhibits an improved turn-on speed and robustness, which are suitable for I/O protection of ESD events in the nanosecond range, particularly the charged-device model(CDM) event.

关键词： diode triggered silicon controlled rectifier(DTSCR) electrostatic discharge(ESD) transmission line pulsing(TLP) very fast transmission line pulsing(VF-TLP) turn-on behavior

Theory and verification of operator design methodology

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Science china(Information Sciences) 2012年第2期55卷 480-490页

作者： HU ZiYi1,ZHAO Yong1,wang XinAn1,HUANG Ru2,wang Teng1 & zhang {3.2 1Key Lab of Integrated Microsystem Science and Engineering Applications,peking university Shenzhen Graduate School,Shenzhen 518055,china 2institute of microelectronics,peking university,Beijing 100871,china 1. Key Lab of Integrated Microsystem Science and Engineering Applications Peking University Shenzhen Graduate School Shenzhen 518055 China2. Institute of Microelectronics Peking University Beijing 100871 China

Non-recurring-engineering(NRE)and time-to-market play an increasingly important role in the field of IC ***,with the continuous development of IC manufacturing technology,it is necessary to propose a novel design methodology to shorten design cycle and enhance design *** this paper,operator design methodology(ODM)is presented and an H.264 encoder is implemented as a *** to the flow of ODM,the register transfer level(RTL)design of H.264 encoder has been accomplished with 15 man-months,which is lower than the average 19 man-months in the field of traditional application specific integrated circuit(ASIC)***,with the advantage of operator design library,the design has a comparable performance with other ASIC *** obtained design can support a real-time video encoding of 720p at 60 frames per second or 1080p at 3. frames per second,working at 167 MHz with SMIC 0.13.μm CMOS *** results provide good evidence for the practicability and efficiency of ODM.

关键词： operator design methodology H.264 encoder integrated circuit hardware

FORWARD GATED-DIODE METHOD FOR EXTRACTING HOT-CARRIER-STRESS-INDUCED BACK INTERFACE TRAPS IN SOI/NMOSFETs

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Journal of Electronics(china) 2002年第3期19卷 332-336页

作者： he Jin zhang xing Huang Ru {3. {3.(institute of microelectronics, peking university, Beijing 100871) institute of microelectronics Peking University Beijing 100871

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.

关键词： Hot-carrier-stress Back interface traps R-G current Gated-diode SOI

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Two-dimensional materials for future information technology: status and prospects

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Science china(Information Sciences) 2024年第6期67卷 1-147页

作者： Hao QIU Zhihao YU Tiange ZHAO Qi zhang Mingsheng XU Peifeng LI Taotao LI Wenzhong BAO Yang CHAI Shula CheN Yiqi CheN Hui-Ming CheNG Daoxin DAI Zengfeng DI Zhuo DONG Xidong DUAN Yuhan FENG Yu FU Jingshu GUO Pengwen GUO Yue HAO Jun he Xiao he Jingyi HU Weida HU Zehua HU Xinyue HUANG Ziyang HUANG Ali IMRAN Ziqiang KONG Jia LI Qian LI Weisheng LI Lei LIAO Bilu LIU Can LIU Chunsen LIU Guanyu LIU Kaihui LIU Liwei LIU Sheng LIU Yuan LIU Donglin LU Likuan MA Feng MIAO Zhenhua NI Jing NING Anlian PAN Tian-Ling REN Haowen SHU Litao SUN Yue SUN Quanyang TAO Zi-Ao TIAN Dong wang Hao wang Haomin wang Jialong wang Junyong wang Wenhui wang xingjun wang Yeliang wang Yuwei wang Zhenyu wang Yao WE... School of Electronic Science and Engineering Nanjing University School of Integrated Circuits Interdisciplinary Research Center for Future Intelligent Chips (Chip-X)Nanjing University School of Integrated Circuit Science and Engineering Nanjing University of Posts and Telecommunications State Key Laboratory of Infrared Physics Shanghai Institute of Technical Physics Chinese Academy of Sciences School of Physics and Key Lab of Quantum Materials and Devices of the Ministry of Education School of Electronic Science & EngineeringSoutheast University College of Integrated Circuits State Key Laboratory of Silicon and Advanced Semiconductor MaterialsZhejiang University Suzhou Laboratory State Key Laboratory of Integrated Chips and Systems School of MicroelectronicsFudan University Shaoxin Laboratory Department of Applied Physics The Hong Kong Polytechnic University Key Laboratory for Micro-Nano Physics and Technology of Hunan Province College of Materials Science and EngineeringHunan University College of Integrated Circuits Zhejiang University Shenzhen Geim Graphene Center Shenzhen Key Laboratory of Layered Materials for Value-Added ApplicationsTsinghua-Berkeley Shenzhen Institute & Institute of Materials ResearchTsinghua Shenzhen International Graduate SchoolTsinghua University State Key Laboratory of Extreme Photonics and Instrumentation College of Optical Science and EngineeringInternational Research Center for Advanced PhotonicsZijingang CampusZhejiang University National Key Laboratory of Materials for Integrated Circuits Shanghai Institute of Microsystem and Information TechnologyChinese Academy of Sciences CAS Key Laboratory of Nanophotonic Materials and Devices & Key Laboratory of Nanodevices and Applications i-LabSuzhou Institute of Nano-Tech and Nano-Bionics (SINANO)Chinese Academy of Sciences College of Chemistry and Chemical Engineering Hunan University Key Laboratory of Quantum State Construction and Manipulation (Ministry of Education) Department of PhysicsRenmin University of China School

Over the past 70 years, the semiconductor industry has undergone transformative changes,largely driven by the miniaturization of devices and the integration of innovative structures and materials. Two-dimensional(2D) materials like transition metal dichalcogenides(TMDs) and graphene are pivotal in overcoming the limitations of silicon-based technologies, offering innovative approaches in transistor design and functionality, enabling atomic-thin channel transistors and monolithic 3. integration. We review the important progress in the application of 2D materials in future information technology, focusing in particular on microelectronics and optoelectronics. We comprehensively summarize the key advancements across material production, characterization metrology, electronic devices, optoelectronic devices, and heterogeneous integration on silicon. A strategic roadmap and key challenges for the transition of 2D materials from basic research to industrial development are outlined. To facilitate such a transition, key technologies and tools dedicated to 2D materials must be developed to meet industrial standards, and the employment of AI in material growth, characterizations, and circuit design will be essential. It is time for academia to actively engage with industry to drive the next 10 years of 2D material research.

关键词： two-dimensional (2D) materials information technology production technology standardization of characterization microelectronic devices optoelectronic devices multi-functional integration

Novel devices and process for 3. nm CMOS technology and beyond

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Science in china(Series F) 2008年第6期51卷 743-755页

作者： wang yangyuan zhang {3. LIU XiaoYan HUANG Ru institute of microelectronics Peking University Beijing 100871 China

The development of next 3. nm generation and below needs innovations on not only device structures, but also fabrication techniques and material selections. Among those promising technologies, new gate structures as high-κ gate dielectric and metal gate, strain channel carrier mobility enhancement technology, and novel non-planar MOSFET structures are all possible candidate technologies. In this paper, we will specify our discussion on the research progress of high-κ-metal gate and non-planar MOSFET-technologies that are suitable to 3. nm technology node and beyond.

关键词： CMOS technology high-k metal gate non-planar MOSFET quasi-ballistic transport

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Scaling Capability of GOI and SOI Devices

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Scaling Capability of GOI and SOI Devices

FORWARD GATED-DIODE R-G CURRENT METHOD: A SIMPLE NOVEL TECHNIQUE FOR CHARACTERIZING LATERAL LIGHTLY DOPING REGION OF LDD MOSFET's

2004 7th International Conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Xia An~* Yi wang Ru Huang xing zhang and {3. wang SOI group institute of microelectronics peking university 100871 Beijing china

＜正＞The scaling capability of germanium-oninsulator （GOI） and silicon-on-insulator（SOI） is *** results suggest that GOI is more suitable for low operating power applications than SOI, and can relax the stringent requirement of the film thickness by up to 160%.Compared with SOI,the channel length limitation of GOI can be relaxed by～3.% with the same film *** intrinsic delay of GOI is smaller than that of *** the same intrinsic delay, the off-state current of GOI is 3.4 orders of magnitude lower than ***,when the channel length scales down below 20nm and the film thickness is smaller than 5nm,GOI loses its advantages over SOI.

关键词： germanium-on-insulator silicon-on-insulator scaling capability low operating power intrinsic delay

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Journal of Electronics(china) 2001年第2期18卷 188-192页

作者： he Jin Huang Aihua zhang xing Huang Ru {3. {3.(institute of Micro-electronics, peking university, Beijing 100871) institute of Micro-electronics Peking UniversityBeijing 100871

This paper presents a simple novel technique-forward gated-diode R-G current method-to determine the lateral lightly-doped source/drain (S/D) region interface state density and effective surface doping concentration of the lightly-doped drain (LDD) N- MOSFET's simultaneously. One interesting result of the numerical analysis is the direct characterization of the interface state density and characteristic gate voltage values corresponding to LDD effective surface doping concentration. It is observed that the S/D N- surface doping concentration and corresponding region's interface state density are R-G current peak position and amplitude dependent, respectively. It is convincible that the proposed method is well suitable for the characterization of deep sub-micron MOSFET's in the current ULSI technology.

关键词： Gated-diode R-G current MOSFET LDD region Interface state Interface state density Characterization

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Design Considerations for Submicron TFD CMOS/SOI Circuits

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Design Considerations for Submicron TFD CMOS/SOI Circuits

The Simulation Analysis of Cross-Talk Behavior in SOI Mixed-Mode Integrated Circuits

1st International Conference on ASIC

作者： Liqiong Wei Yuhua Cheng xing zhang Yingxue Li and {3. {3. institute of microelectronics peking university Beijing 100871 P.R.china

＜正＞ A more accurate and comprehensive physical model is described and used to analyse the characteristics of submicron TFD CMOS/SOI devices and circuits. Considering the constraint parameters such as breakdown voltage, source/drain parasitic resistance, propagation delay time and saturation current, et al., an optimized design region for TFD CMOS/SOI circuits is presented.

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The Simulation Analysis of Cross-Talk Behavior in SOI Mixed-...