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功能材料 2000年第3期31卷 273-275页

作者：全宝富金丽妍全海英戚金清孙良彦吉林大学电子工程系吉林长春130023

采用溶胶 -凝胶及共沉淀技术制备了低阻SnO2 微粉。利用XRD及SEM技术分析了SnO2 微粉的结构及形貌。利用这种低阻SnO2 制作的平面热线式气敏元件对H2 、NH3 具有较好的气敏特性。

关键词：低阻SnO2 气敏特性溶胶-凝胶法共沉淀技术

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基于人工智能的韩国语教育研究

韩国语教学与研究 2020年第1期 59-67页

作者：金丽妍鲁东大学

2016年3月9日,韩国的围棋天才李世石以1:4的总比分败给了人工智能棋手阿尔法,这让全世界受到了很大的冲击,并让人类意识到人工智能时代的到来。人工智能的发展不仅在围棋界,在金融、科学、医疗、新闻、教育等方面也有着突飞猛进的发展... 详细信息

2016年3月9日,韩国的围棋天才李世石以1:4的总比分败给了人工智能棋手阿尔法,这让全世界受到了很大的冲击,并让人类意识到人工智能时代的到来。人工智能的发展不仅在围棋界,在金融、科学、医疗、新闻、教育等方面也有着突飞猛进的发展。本文的研究目的在于把人工智能用于韩语教育当中,以期为韩语学习者提供有效的学习方法。

关键词：人工智能韩语的需求韩语教育韩国语的听、说、读、写

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韩语教学中翻转课堂教学模式的运用研究

韩国语教学与研究 2022年第2期 86-91页

作者：金丽妍鲁东大学蔚山船舶与海洋学院

随着信息技术的不断进步,新的课程教学理念不断做出相应的更新改变。在高校韩语课程中应用上翻转课堂,就是针对教育教学模式进行改革。翻转课堂可以将传统的教学方法和新兴的教学手段结合起来,重点讲解教学内容,激发学生兴趣。本文试图... 详细信息

随着信息技术的不断进步,新的课程教学理念不断做出相应的更新改变。在高校韩语课程中应用上翻转课堂,就是针对教育教学模式进行改革。翻转课堂可以将传统的教学方法和新兴的教学手段结合起来,重点讲解教学内容,激发学生兴趣。本文试图阐述翻转课堂的定义与内涵,分析翻转课堂在高校韩语教学的应用优势,提出在高校韩语教学中如何运用翻转课堂模式,发挥其作用,以便更好地适应当前教育趋势的变化。

关键词：韩语教学翻转课堂翻转课堂模式韩语教育

关于在韩国语教育中先语末语尾‘’的扩张使用

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韩国语教学与研究 2015年第1期 52-62页

作者：金丽妍 [韩国]中央大学

一直以来在语言学中，先语末语尾“ ”是待遇主体与主语相应，连接在表现某种动作或状态的动词或者形容词的谓语语间使用的语尾来规定，主要使用在主体敬语法。但是随着时代与语言使用的变化和服务业的发达，用语法分析时先语末语尾“ ... 详细信息

一直以来在语言学中，先语末语尾“ ”是待遇主体与主语相应，连接在表现某种动作或状态的动词或者形容词的谓语语间使用的语尾来规定，主要使用在主体敬语法。但是随着时代与语言使用的变化和服务业的发达，用语法分析时先语末语尾“ ”有着听者待遇的机能，待遇对象渐渐适用于主体与事物。因此以往的先语末语尾“ ”的语法渐渐动摇，甚至被越来越多的人群广泛使用。本篇论文以分析先语末语尾“ ”的扩张使用作为目的，具体分析先语末语尾“ ”与谓语的结合，与“ ”的结合，设定时与谓语的结合，与被动词和形容词的结合，与所有一所在句“ ”的结合，与“ ”的结合，还有与系词句结合的例文。敬语法是因话者的意图来随意使用的，因此本文详细分析敬语的战略用法和在文章里先语末语尾“ ”的重复使用，再分析韩国语教育方面是怎样看待这种语法现象，再为韩国语教学提出几点建议。

关键词：敬语法的过度待遇先语末语尾“ ” 听者待遇待遇对象

Design of logic process based low-power 512-bit EEPROM for UHF RFID tag chip

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Journal of Central South University 2010年第5期17卷 1011-1020页

作者：金丽妍 LEE J H KIM Y H Department of Electronic Engineering Changwon National University

A 512-bit EEPROM IP was designed by using just logic process based *** limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were *** addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving ***,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were *** reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was *** result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.

关键词： electrically erasable programmable read-only memory (EEPROM) logic process DC-DC converter ring oscillator sequential pumping scheme dual oscillation period radio frequency identification (RFID)

Design of 1 kbit antifuse one time programmable memory IP using dual program voltage

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Journal of Central South University 2011年第1期18卷 125-132页

作者：金丽妍 JANG Ji-Hye KIM Du-Hwi KIM Young-Hee Department of Electronic Engineering Changwon National University9 Sarim-DongChangwon 641-773Korea

A 1 kbit antifuse one time programmable(OTP) memory IP,which is one of the non-volatile memory IPs,was designed and used for power management integrated circuits(ICs).A conventional antifuse OTP cell using a single positive program voltage(VPP) has a problem when applying a higher voltage than the breakdown voltage of the thin gate oxides and at the same time,securing the reliability of medium voltage(VM) devices that are thick gate transistors.A new antifuse OTP cell using a dual program voltage was proposed to prevent the possibility for failures in a qualification test or the yield *** the newly proposed cell,a stable sensing is secured from the post-program resistances of several ten thousand ohms or below due to the voltage higher than the hard breakdown voltage applied to the terminals of the *** layout size of the designed 1 kbit antifuse OTP memory IP with Dongbu HiTek's 0.18 μm Bipolar-CMOS-DMOS(BCD) process is 567.9 μm×205.135 μm and the post-program resistance of an antifuse is predicted to be several ten thousand ohms.

关键词： one time programmable memory IP antifuse hard breakdown dual program voltage post-program resistance

Design of 512-bit logic process-based single poly EEPROM IP

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Journal of Central South University 2011年第6期18卷 2036-2044页

作者：金丽妍 JANG Ji-Hye 余忆宁 HA Pan-Bong KIM Young-Hee Department of Electronic Engineering Changwon National University

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.

关键词： single poly EEPROM cell Fowler-Nordheim tunneling logic process radio frequency identification small area

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硅基热线式气敏元件及其特性

传感技术学报 1999年第3期12卷 206-209页

作者：全宝富金丽妍金海英孙良彦孙承松吉林大学电子工程系长春130023 沈阳工业大学电子工程系沈阳110023

利用射频溅射在硅衬底上制作Ｐｔ膜电极，以溶胶－凝胶法制作的低阻ＳｎＯ２为敏感层制成平面热线式气敏元件．研究了工艺条件、掺杂行为及其对气敏特性的影响．掺Ｓｂ（３％ａｔｍ）及Ｐｔ石棉（２％ｗｔ）在７００℃烧结１． ... 详细信息

利用射频溅射在硅衬底上制作Ｐｔ膜电极，以溶胶－凝胶法制作的低阻ＳｎＯ２为敏感层制成平面热线式气敏元件．研究了工艺条件、掺杂行为及其对气敏特性的影响．掺Ｓｂ（３％ａｔｍ）及Ｐｔ石棉（２％ｗｔ）在７００℃烧结１．５ｈ的元件对Ｈ２、ＮＨ３灵敏度较高。

关键词：气敏元件硅平面热线式气敏特性

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

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Journal of Central South University 2012年第1期19卷 168-173页

作者： JANG Ji-Hye 金丽妍 JEON Hwang-Gon KIM Kwang-Il HA Pan-Bong KIM Young-Hee Department of Electronic Engineering Changwon National University9 Sarim-DongChangwon 641-773Korea

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 ~tm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm ×100.15μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.

关键词： eFuse differential paired efuse cell one time programmable memory sensing resistance D flip-flop based sense amplifier

Design of small-area and high-efficiency DC-DC converter for 1 T SRAM

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Journal of Central South University 2012年第2期19卷 417-423页

作者： LEE Jae-hyung 金丽妍余忆宁 JANG Ji-hye KIM Kwang-il HA Pan-bong KIM Young-hee Department of Electronic Engineering Changwon National University9 Sarim-Dong

The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.

关键词： 1 T-static random access memory direct current-direct current converter positive word-line voltage negative word-line voltage half- VDb generator