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Comparison between N_2 and O_2 anneals on the integrity of an Al_2O_3/Si_3N_4/SiO_2/Si memory gate stack

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Chinese Physics B 2014年第8期23卷 172-176页

作者：褚玉琼张满红霍宗亮刘明 Institute of Microelectronics Chinese Academy of Sciences School of Electrical and Electronic Engineering North China Electric Power University

In this paper the endurance characteristics and trap generation are investigated to study the effects of different postdeposition anneals （PDAs） on the integrity of an Al2O3/Si3N4/SiOz/Si memory gate stack. The flat-band voltage （Vfb） turnarounds are observed in both the programmed and erased states of the N2-PDA device. In contrast, this turnaround is observed only in the erased state of the O2-PDA device. The Vfb in the programmed state of the O2-PDA device keeps increasing with increasing program/erase （P/E） cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O2-PDA device two extra types of trap are also found： the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.

关键词： charge trapping memory post deposition anneal endurance traps

Energy Dependence of Interface Trap Density——Investigated by Relaxation Spectral Technique

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Journal of Semiconductors 2003年第1期24卷 18-23页

作者：霍宗亮毛凌锋谭长华许铭真北京大学微电子学研究所北京100871

According to the definition of interface traps,a new application of relaxation spectral technique to sub-threshold swing shift and sub-threshold gate voltage shift is proposed to extract interface trap density in 1.9nm *** thus the energy distribution of interface trap can be *** to the two methods,the energy profile of interface traps agrees with those reported in *** to other methods,this method is simpler and more convenient.

关键词： relaxation spectral technique interface trap MOS structure

Multi-Defect Generation Behavior in Ultra Thin Oxide Under DT Stresses

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Journal of Semiconductors 2003年第2期24卷 127-132页

作者：霍宗亮毛凌锋谭长华许铭真北京大学微电子学研究所北京100871

The saturation behavior of stress current is *** three types of precursor sites for trap generation are also introduced by fitting method based on first order rate equation.A further investigation by statistics experiments shows that there are definite relationships among time constant of trap generation,the time to breakdown,and stress *** also means that the time constant of trap generation can be used to predict oxide *** method is faster for TDDB study compared with usual breakdown experiments.

关键词： defect MOS structure time dependence dielectric breakdown

基于FLASH-March算法的FLASH缺陷检测系统

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微电子学与计算机 2014年第10期31卷 81-85页

作者：郭进杰王瑜李婷霍宗亮中国科学院微电子所北京100029

介绍了FLASH缺陷机理并提出了面向8bit和16bit的FLASH-March算法,在此基础上设计并实现一种新的FLASH缺陷检测系统.该系统以FPGA为硬件基础,以Microblaze软核为CPU搭建系统主体架构,实现了对FLASH缺陷的检测.相比于传统方法,本系统有实... 详细信息

介绍了FLASH缺陷机理并提出了面向8bit和16bit的FLASH-March算法,在此基础上设计并实现一种新的FLASH缺陷检测系统.该系统以FPGA为硬件基础,以Microblaze软核为CPU搭建系统主体架构,实现了对FLASH缺陷的检测.相比于传统方法,本系统有实现简单,成本低,便于相关算法研究的特点.本设计最终在实际中得到应用,验证了设计的有效性和可靠性.

关键词： FLASH 缺陷 FLASH-March算法 FPGA

Investigation of Gate Defects in Ultrathin MOS Structures Using DTRS Technique

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Journal of Semiconductors 2002年第11期23卷 1146-1153页

作者：霍宗亮杨国勇许铭真谭长华段小蓉北京大学微电子学研究所北京100871

s:A detailed description of relaxation spectroscopy technique under direct tunneling stress is given.A double peak phenomena by applied relaxation spectroscopy on ultra thin (4nm) under FN stress,and the centroid of ... 详细信息

关键词： tunneling metal oxide semiconductor device proportional difference operator

一种用于NAND闪存的奇偶位线块编程补偿算法

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微电子学 2018年第4期48卷 500-503页

作者：门顶顶曹华敏王颀霍宗亮中国科学院大学北京100049 中国科学院物联网研究发展中心江苏无锡214135 中国科学院微电子研究所北京100029

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编... 详细信息

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。

关键词： NAND闪存数据保持编程干扰阈值漂移补偿可靠性

Improved charge trapping flash device with Al_2O_3 /HfSiO stack as blocking layer

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Chinese Physics B 2011年第10期20卷 476-479页

作者：郑志威霍宗亮朱晨昕许中广刘璟刘明 Laboratory of Nano-Fabrication and Novel Devices Integrated Technology Institute of Microelectronics Chinese Academy of Sciences

In this paper, we investigate an Al2O3/HfSiO stack as the blocking layer of a metal-oxide-nitride-oxide-silicon- type （MONOS） memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al2O3/HfO2 stack as the blocking layer, the sample with the Al2O3/HfSiO stack as the blocking layer shows high program/erase （P/E） speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al2O3/HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications.

关键词： charge trapping flash blocking layer stack

A high efficiency all-PMOS charge pump for 3D NAND flash memory

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Journal of Semiconductors 2016年第7期37卷 98-103页

作者：付丽银王瑜王颀霍宗亮 Institute of Microelectronics Chinese Academy of Sciences

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pellieoni structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.

关键词： charge pump circuit high power efficiency peripheral circuit design 3D vertical NAND flash memory

适用于3D NAND的高稳定度的Capacitor-free LDO

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现代电子技术 2019年第24期42卷 42-45页

作者：万金梅刘飞曾子玉霍宗亮中国科学院大学北京100029 中国科学院大学微电子研究所北京100029 长江存储科技有限责任公司湖北武汉430078

文中设计一种应用于3D NAND的无片外补偿电容的LDO,该电路在传统嵌套米勒补偿的基础上,增加"gm减小电路"和"轻重载控制电路",实现在空载(电流负载为零)且有大负载电容条件下的稳定。此设计应用YMTC 0.18μm工艺实现,仿真结果显示,在2.5~... 详细信息

文中设计一种应用于3D NAND的无片外补偿电容的LDO,该电路在传统嵌套米勒补偿的基础上,增加"gm减小电路"和"轻重载控制电路",实现在空载(电流负载为零)且有大负载电容条件下的稳定。此设计应用YMTC 0.18μm工艺实现,仿真结果显示,在2.5~3.6 V电源供电下,整个电路消耗的静态电流为50μA,总补偿电容为7 pF,电路稳定的时间小于6μs,输出线性调整率小于2.2 mV/V,负载调整率小于0.9 mV/mA。

关键词： LDO 米勒补偿 3D NAND 电路设计仿真实验稳定性分析