Development of three-dimensional MOS structures from trench-capacitor DRAM cell to pillar-type transistor
作者单位：Hiroshima UniversityResearch Institute for Nanodevice and Bio Systems 1-4-2 KagamiyamaHigashi-hiroshimaHiroshima 739-8527Japan
会议名称：《2008 9th International Conference on Solid-State and Integrated-Circuit Technology》
会议日期：2008年
学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学]
关 键 词：[IEEE Keyword]Technological innovation Microprocessors Logic gates Computer architecture Transistors Capacitors Random access memory
摘 要：The author invented a trench-capacitor dynamic -random-access memory （DRAM） cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide- semiconductor （MOS） structure. Subsequent to this trial various kinds of vertical-channel MOS transistors have been proposed in integrated circuits field. This presentation will describe circumstances of inven- tion and development of the trench-capacitor DRAM cell and subsequent development of several vertical-channel MOS transistors done by the author’s group.