A Fast FPGA Implementation for Triple DES Encryption Scheme

作     者：Edni Del Rosal Sanjeev Kumar 

作者机构：IEEE Network Security Research Lab Department of Electrical/Computer Engineering The University of Texas Rio Grande Valley Edinburg USA 

出 版 物：《Circuits and Systems》 (电路与系统（英文）)

年 卷 期：2017年第8卷第9期

页      面：237-246页

学科分类：0810[工学-信息与通信工程] 08[工学] 081001[工学-通信与信息系统] 

主　　题：Data Encryption Standard Triple DES DES TDES 3DES Non-Pipelined Pipelined Cyclone II FPGA VHDL 

摘      要：In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock;a performance increase of up to 16 times.