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Response of solenopsis invicta （Hymenoptera： Formicidae） to potassium oleate water solution

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Insect science 2010年第2期17卷 121-128页

作者： Jian Chen Han-Wu shang Xixuan Jin Biological Control of Pests Research unit Agricultural Research Service U.S. Department of Agriculture Stoneville Mississippi USA College of Life sciences China Jiliang University Hangzhou China

In contrast to floating on the surface of distilled water, ants were immediately submerged after being placed in the potassium oleate （PO） water solution, which led to immobilization within minutes. However, some workers survived after being immersed in 0.03% PO water solution at 25℃ for up to 640 rnin. Elevated temperature of the PO water solution is needed to kill ants within a shorter time frame. At 50℃ and 0.13% PO concentration, total mortality was achieved with 10-min immersion for all ants, including brood and adult ants. soil has a negative effect on the effectiveness of potassium oleate; however, such negative effect can be overcome by increasing either treatment temperature or duration of the treatment. In addition to immobilizing and lethal effect, PO repels ants. PO may have the potential to be incorporated into immersion treatment for the quarantine of imported fire ants to reduce the use of synthetic contact insecticides.

关键词： dipping immersion treatment quarantine soap surfactant

simultaneous Minimization of Capacity and Conflict Misses

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Journal of Computer science & Technology 2007年第4期22卷 497-504页

作者：李致远 department of Computer sciences Purdue UniversityWest LafayetteIN 47907U.S.A.

Loop tiling （or loop blocking） is a well-known loop transformation to improve temporal locality in nested loops which perform matrix computations. When targeting caches that have low associativities, one of the key challenges for loop tiling is to simultaneously minimize capacity misses and conflict misses. This paper analyzes the effect of the tile size and the array-dimension size on capacity misses and conflict misses. The analysis supports the approach of combining tile-size selection （to minimize capacity misses） with array padding （to minimize conflict misses）.

关键词： caches optimizing compilers loop transformation array padding

Hetero-DB： Next Generation High-Performance Database systems by Best utilizing Heterogeneous Computing and storage Resources

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Journal of Computer science & Technology 2015年第4期30卷 657-678页

作者：张凯陈峰丁晓宁槐寅李如豹罗天王凯博袁源张晓东 department of Computer science and Technology University of Science and Technology of China Hefei 230027 China department of Computer science and Engineering The Ohio State University Columbus OH 43210 U.S.A. department of Computer science and Engineering Louisiana State University Baton Rouge LA 70803 U.S.A. department of Computer science New Jersey Institute of Technology Newark NJ 07102 U.S.A. Databricks Inc. San Francisco CA 94105 U.S.A. VMware Inc. Palo Alto CA 94304 U.S.A.

With recent advancement on hardware technologies, new general-purpose high-performance devices have been widely adopted, such as the graphics processing unit （GPu） and solid state drive （ssD）. GPu may offer an order of higher throughput for applications with massive data parallelism, compared with the multicore CPu. Moreover, new storage device ssD is also capable of offering a much higher I/O throughput and lower latency than a traditional hard disk device （HDD）. These new hardware devices can significantly boost the performance of many applications;thus the database community has been actively engaging in adopting them into database systems. However, the performance benefit cannot be easily reaped if the new hardwares are improperly used. In this paper, we propose Hetero-DB, a high-performance database system by exploiting both the characteristics of the database system and the special properties of the new hardware devices in system’s design and implementation. Hetero-DB develops a GPu-aware query execution engine with GPu device memory management and query scheduling mechanism to support concurrent query execution. Furthermore, with the ssD-HDD hybrid storage system, we redesign the storage engine by organizing HDD and ssD into a two-level caching hierarchy in Hetero-DB. To best utilize the hybrid hardware devices, the semantic information that is critical for storage I/O is identified and passed to the storage manager, which has a great potential to improve the e？ciency and performance. Hetero-DB aims to maximize the performance benefits of GPu and ssD, and demonstrates the effectiveness for designing next generation database systems.

关键词： database heterogeneous system GPu ssD

Feature-Preserving Mesh Denoising via Anisotropic surface Fitting

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Journal of Computer science & Technology 2012年第1期27卷 163-173页

作者：汪俊余泽云 department of Computer science University of Wisconsin Milwaukee WI 53211 U.S.A.

We propose in this paper a robust surface mesh denoising method that can effectively remove mesh noise while faithfully preserving sharp features. This method utilizes surface fitting and projection techniques. sharp features are preserved in the surface fitting algorithm by considering an anisotropic neighborhood of each vertex detected by the normal-weighted distance. In addition, to handle the mesh with a high level of noise, we perform a pre-filtering of surface normals prior to the neighborhood searching. A number of experimental results and comparisons demonstrate the excellent performance of our method in preserving important surface geometries while filtering mesh noise.

关键词： mesh denoising feature-preserving surface fitting anisotropic filtering

BACH： A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories

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Journal of Computer science & Technology 2016年第1期31卷 20-35页

作者： Jishen Zhao Cong Xu Tao Zhang Yuan Xie department of Computer Engineering University of California at Santa Cruz Santa Cruz CA 95064 U.S.A. Hewlet-Packard Labs Palo Alto CA 94304 U.S.A. NVIDIA Corporation Santa Clara CA 95050 U.S.A. department of Electrical and Computer Engineering University of California at Santa Barbara Santa Barbara CA 93106 U.S.A.

Limited main memory bandwidth is becoming a fundamental performance bottleneck in chipmultiprocessor （CMP） design. Yet directly increasing the peak memory bandwidth can incur high cost and power consumption. In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies. Components of our BACH design include a hybrid cache hierarchy, a reconfiguration mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory （sTT-MRAM）, resistive memory （ReRAM）, and embedded DRAM （eDRAM）, to configure each level so that the peak bandwidth of the overall cache hierarchy is optimized. Our reconfiguration mechanism can dynamically adjust the cache capacity of each level based on the predicted bandwidth demands of running workloads. The bandwidth prediction is performed by our prediction engine. We evaluate the system performance gain obtained by BACH design with a set of multithreaded and multiprogrammed workloads with and without the limitation of system power budget. Compared with traditional sRAM-based cache design, BACH improves the system throughput by 58% and 14% with multithreaded and multiprogrammed workloads respectively.

关键词： memory bandwidth hybrid cache reconfigurable cache nonvolatile memory

ROPAs:Cross-Layer Cognitive Architecture for Mobile uWB Networks

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Journal of Computer science & Technology 2008年第3期23卷 413-425页

作者： Chittabrata Ghosh Dharma P.Agrawal department of Computer science University of CincinnatiCincinnatiOH-45221U.S.A.

The allocation of bandwidth to unlicensed users, without significantly increasing the interference on the existing licensed users, is a challenge for ultra Wideband （uWB） networks. Our research work presents a novel Rake Optimization and Power Aware scheduling （ROPAs） architecture for uWB networks. since uWB communication is rich in multipath effects, a Rake receiver is used for path diversity. Our idea of developing an optimized Rake receiver in our ROPAs architecture stems from the intention of reducing the computation complexity in terms of the number of multiplications and additions needed for the weight derivation attached to each finger of the Rake receiver. Our proposed work uses the Cognitive Radio （CR） for dynamic channel allocation among the requesting users while limiting the average power transmitted in each sub-band. In our proposed novel ROPAs architecture, dynamic channel allocation is achieved by a CR-based cross-layer design between the PHY and Medium Access Control （MAC） layers. Additionally, the maximum number of parallel transmissions within a frame interval is formulated as an optimization problem. This optimal decision is based on the distance parameter between a transmitter-receiver pair, bit error rate and frequency of request by a particular application. Moreover, the optimization problem improvises a differentiation technique among the requesting applications by incorporating priority levels among user applications. This provides fairness and higher throughput among services with varying power constraint and data rates required for a uWB network.

关键词： cognitive radio joint power and frequency allocation power aware scheduling primary and secondary users,ultra wideband

I/O Acceleration via Multi-Tiered Data Buffering and Prefetching

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Journal of Computer science & Technology 2020年第1期35卷 92-120页

作者： Anthony Kougkas Hariharan Devarajan Xian-He sun department of Computer science Illinois Institute of TechnologyChicago 60616U.S.A

Modern High-Performance Computing(HPC)systems are adding extra layers to the memory and storage hierarchy,named deep memory and storage hierarchy(DMsH),to increase I/O *** hardware technologies,such as NVMe and ssD,have been introduced in burst buffer installations to reduce the pressure for external storage and boost the burstiness of modern I/O *** DMsH has demonstrated its strength and potential in ***,each layer of DMsH is an independent heterogeneous system and data movement among more layers is significantly more complex even without considering *** to efficiently utilize the DMsH is a subject of research facing the HPC ***,accessing data with a high-throughput and low-latency is more imperative than *** prefetching is a well-known technique for hiding read latency by requesting data before it is needed to move it from a high-latency medium(e.g.,disk)to a low-latency one(e.g.,main memory).However,existing solutions do not consider the new deep memory and storage hierarchy and also suffer from under-utilization of prefetching resources and unnecessary ***,existing approaches implement a client-pull model where understanding the application's I/O behavior drives prefetching *** towards exascale,where machines run multiple applications concurrently by accessing files in a workflow,a more data-centric approach resolves challenges such as cache pollution and *** this paper,we present the design and implementation of Hermes:a new,heterogeneous-aware,multi-tiered,dynamic,and distributed I/O buffering *** enables,manages,supervises,and,in some sense,extends I/O buffering to fully integrate into the *** introduce three novel data placement policies to efficiently utilize all layers and we present three novel techniques to perform memory,metadata,and communication management in hierarchical buffering ***,we demonstrate the benefits

关键词： I/O buffering heterogeneous buffering layered buffering deep memory hierarchy burst buffers hierarchical data prefetching data-centric architecture

The Memory-Bounded speedup Model and Its Impacts in Computing

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Journal of Computer science & Technology 2023年第1期38卷 64-79页

作者：孙贤和鲁潇阳 department of Computer science Illinois Institute of TechnologyChicago 60616U.S.A.

With the surge of big data applications and the worsening of the memory-wall problem,the memory system,instead of the computing unit,becomes the commonly recognized major concern of ***,this“memorycentric”common understanding has a humble *** than three decades ago,the memory-bounded speedup model is the first model recognizing memory as the bound of computing and provided a general bound of speedup and a computing-memory trade-off *** memory-bounded model was well received even by *** was immediately introduced in several advanced computer architecture and parallel computing textbooks in the 1990’s as a must-know for scalable *** include *** Hwang’s book“scalable Parallel Computing”in which he introduced the memory-bounded speedup model as the sun-Ni’s Law,parallel with the Amdahl’s Law and the Gustafson’s *** the years,the impacts of this model have grown far beyond parallel processing and into the fundamental of *** this article,we revisit the memory-bounded speedup model and discuss its progress and impacts in depth to make a unique contribution to this special issue,to stimulate new solutions for big data applications,and to promote data-centric thinking and rethinking.

关键词： memory-bounded speedup scalable computing memory-wall performance modeling and optimization data-centric design

Fish vaccines:current state and future trends

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Fish vaccines:current state and future trends