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A low power cyclic ADC design for a wireless monitoring system for orthopedic implants

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Journal of Semiconductors 2009年第8期30卷 147-152页

作者：陈怡李福乐陈虹张春王志华 tsinghua National Laboratory for Information Science and Technology Institute of MicroelectronicsTsinghua University

This paper presents a low power cyclic analog-to-digital convertor （ADC） design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks （MDACs） and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully op- timized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation （UMC） 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.

关键词： monitoring system low power consumption small size analog to digital convertor single to differential convertor

Deep brain-machine interfaces:sensing and modulating the human deep brain

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National Science Review 2022年第10期9卷 19-33页

作者： Yanan Sui Huiling Yu Chen Zhang Yue Chen Changqing Jiang Luming Li National Engineering Research Center of Neuromodulation Tsinghua University Precision Medicine & Healthcare Research Center Tsinghua-Berkeley Shenzhen Institute Tsinghua University IDG/Mc Govern institute for Brain Research at tsinghua University institute of Epilepsy Beijing Institute for Brain Disorders

Different from conventional brain-machine interfaces that focus more on decoding the cerebral cortex,deep brain-machine interfaces enable interactions between external machines and deep brain *** sense and modulate deep brain neural activities,aiming at function restoration,device control and therapeutic *** this article,we provide an overview of multiple deep brain recording and stimulation techniques that can serve as deep brain-machine *** highlight two widely used interface technologies,namely deep brain stimulation and stereotactic electroencephalography,for technical trends,clinical applications and brain connectivity *** discuss the potential to develop closed-loop deep brain-machine interfaces and achieve more effective and applicable systems for the treatment of neurological and psychiatric disorders.

关键词： deep brain-machine interface sensing and modulation deep brain stimulation stereotactic electroencephalography

A 5.8 GHz class-AB power amplifier with 25.4 d Bm saturation power and 29.7% PAE

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Science China(Information Sciences) 2017年第4期60卷 191-195页

作者： Chuan QIN Lei ZHANG Li ZHANG Yan WANG Zhiping YU institute of Microelectronics Tsinghua University

In this paper, an effective and succinct radio-frequency(RF) grounding technique for class-AB power amplifier(PA) is presented. The proposed technique employs a grounding path, resonant with a capacitor in series at the center of the fundamental and second-order harmonic frequencies, between the critical ground nodes, to ensure a low impedance path. The power loss due to imperfect grounding is then reduced by 2 d B,and the saturated output power and power added efficiency(PAE) are therefore significantly improved. A fully integrated 5.8-GHz PA with the proposed technique is designed and implemented in a 65-nm CMOS *** result shows a saturated output power of 25.4 d Bm and a peak PAE of 29.7%, while with only 2.5 V of supply voltage.

关键词： power amplifier class AB high efficiency fully integrated CMOS

Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

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Journal of Semiconductors 2010年第10期31卷 57-61页

作者：古海明潘立阳祝鹏伍冬张志刚许军 institute of Microelectronics Tsinghua University

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory （NUC-CTM） device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect （SBE） and provide 3-bit per cell capability. Owing to the n- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.

关键词： multi-bit storage non-uniform channel charge trapping memory NAND array SiON layer

A 13-bit, 8 MSample/s pipeline A/D converter

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Journal of Semiconductors 2009年第2期30卷 69-73页

作者：郭丹丹李福乐张春王志华 institute of Microelectronics Tsinghua University

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.

关键词： analog-to-digital converter pipeline high-accuracy sampling circuit power programmable

Impacts of additive uniaxial strain on hole mobility in bulk Si and strained-Si p-MOSFETs

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Journal of Semiconductors 2009年第10期30卷 27-32页

作者：赵硕郭磊王敬许军刘志弘 tsinghua National Laboratory for Information Science and Technology Institute of MicroelectronicsTsinghua University

Hole mobility changes under uniaxial and combinational stress in different directions are characterized and analyzed by applying additive mechanical uniaxial stress to bulk Si and SiGe-virtual-substrate-induced strained- Si（s-Si）p-MOSFETs（metal-oxide-semiconductor field-effect transistors）along 110 and 100 channel directions. In bulk Si,a mobility enhancement peak is found under uniaxial compressive strain in the low vertical *** combination of 100 direction uniaxial tensile strain and substrate-induced biaxial tensile strain provides a higher mobility relative to the 110 direction,opposite to the situation in bulk *** the combinational strain experiences a gain loss at high field,which means that uniaxial compressive strain may still be a better *** mobility enhancement of SiGe-induced strained p-MOSFETs along the 110 direction under additive uniaxial tension is explained by the competition between biaxial and shear stress.

关键词： hole mobility enhancement additive uniaxial strain biaxial strain combinational strain channeldirection

LSB page refresh based retention error recovery scheme for MLC NAND Flash

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Science China(Information Sciences) 2016年第4期59卷 121-131页

作者： Haozhi MA Lifang LIU Liyang PAN Jun XU institute of Microelectronics Tsinghua University tsinghua National Laboratory for Information Science and Technology

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell(MLC) technology. High retention error rate in highly program/erase(P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit(LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

关键词： NAND flash reliability retention refresh data error recovery

Feature Scale Simulation of PECVD of SiO_2 in SiH_4/N_2O Mixture

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Plasma Science and Technology 2014年第4期16卷 385-389页

作者：刘璇葛婕杨轶宋亦旭任天令 institute of Microelectronics Tsinghua University

In this paper, to simulate the process of PECVD （plasma enhanced chemical vapor deposition） of SiO2, the plasma chemistry and plasma density of SiH4/N2O mixture have been studied with an inductive coupled plasma model, and the level set methodology has been used to obtain the feature scale variation during the process. In this simulation, the goal is to fill a trench. We studied how ion sputtering and chamber pressure affect the feature scale model. After the simulation, we found that the trench will close up at the top after a few steps, and if we add the ion sputtering into the surface reactions, the trench top will close up a little later. When the chamber pressure is improved, the plasma density will increase, so the trench top will close up earlier. In semiconductor device manufacture, people can control the trench＇s feature scale through adjusting these two parameters.

关键词： deposition plasma feature scale simulation

A low cost integrated transceiver for mobile UHF passive RFID reader applications

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Journal of Semiconductors 2009年第9期30卷 86-90页

作者：王敬超张春池保勇王自强李福乐王志华 institute of Microelectronics Tsinghua University

A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.

关键词： UHF RFID reader single chip transceiver