A low power cyclic ADC design for a wireless monitoring system for orthopedic implants

作     者：陈怡 李福乐 陈虹 张春 王志华 

作者机构：Tsinghua National Laboratory for Information Science and TechnologyInstitute of MicroelectronicsTsinghua University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2009年第30卷第8期

页      面：147-152页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080401[工学-精密仪器及机械] 0804[工学-仪器科学与技术] 080402[工学-测试计量技术及仪器] 0838[工学-公安技术] 

基　　金：supported by the National Natural Science Foundation of China(No.60475018) 

主　　题：monitoring system low power consumption small size analog to digital convertor single to differential convertor 

摘      要：This paper presents a low power cyclic analog-to-digital convertor （ADC） design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks （MDACs） and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully op- timized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation （UMC） 0.18-μm 1P6M CMOS process. The core of the ADC occupies only 0.12 mm2. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 μW in normal working mode and less than 150 nW in sleep mode.