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A new FPGA architecture suitable for DSP applications

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Journal of Semiconductors 2011年第5期32卷 140-145页

作者：王丽云来金梅童家榕唐璞山陈星段雪岩陈利光王健王元 asic and system state key laboratory Fudan University

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX （multiplexer） is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm^2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

关键词： FPGA uniform GRM structure DSP modules

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

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Journal of Semiconductors 2011年第7期32卷 62-69页

作者：赵裔王申杰秦亚杰洪志良 state key laboratory of asic and system Fudan University

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is *** challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist *** paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 *** this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise *** measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/*** core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^*** ADC achieves a figure of merit of 3.75 pJ/conversion-step.

关键词： flash ADC sub-sampling track and hold amplifier resistive averaging technique comparator IR-UWB

A 900 MHz,21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

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Journal of Semiconductors 2010年第12期31卷 116-122页

作者：韩科锋曹圣国谈熙闫娜王俊宇唐长文闵昊 state key laboratory of asic & system Fudan University

A two-stage differential linear power amplifier （PA） fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency （PAE） is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. system measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.

关键词： CMOS power amplifier PAE power matching RFID reader

A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems

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Journal of Semiconductors 2011年第1期32卷 79-84页

作者：张辉秦亚杰杨思宇洪志良 state key laboratory of asic & system fudan university

An ultra-low power 12 bits 2 kS/s successive approximation register analog-to-digital converter （ADC） is presented. For power optimization, the voltage supply of the digital part is lowered, and the offset voltage of the latch is self-calibrated. Targeted for better linearity and lower noise, an improved digital-to-analog converter capacitor array layout strategy is presented, and a low kick-back noise latch is proposed. The chip was fabricated by using 0.18μm 1P6M CMOS technology. The ADC achieves 61.8 dB SNDR and dissipates 455 nW only, resulting in a figure of merit of 220 fJ/conversion-step. The ADC core occupies an active area of only 674 ×639μm2.

关键词： ADC SAR low power biopotential acquisition system

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

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Journal of Semiconductors 2010年第9期31卷 134-140页

作者：张章袁宇丹郭亚炜程旭曾晓洋 state key laboratory of asic & system Fudan University

A 10-bit 30-MS/s pipelined analog-to-digital converter（ADC） is *** the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage *** results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7- MHz input *** FoM is 0.33 pJ/*** peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,*** ADC core area is 0.94 mm^2.

关键词： analog-to-digital converter pipelined sampling capacitor two-stage op amp compensation linearity of analog switch sub-1-V bandgap voltage reference

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

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Journal of Semiconductors 2011年第12期32卷 121-127页

作者：郝诗磊梅年松黄煜梅洪志良 state key laboratory of asic and system Fudan University

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consump- tion at low gain mode. The front-end chip is manufactured on a 0.13-#m CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.

关键词： 5GHz balun LNA capacitive cross-coupling current mode passive mixer current mode switching

A 16.3 p J/pulse low-complexity and energy-efficient transmitter with adjustable pulse parameters

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Journal of Semiconductors 2011年第6期32卷 119-125页

作者：蒋俊赵裔邵轲陈虎夏伶俐洪志良 state key laboratory of asic and system Fudan University

This paper presents a novel,fully integrated transmitter for 3-5 GHz pulsed *** BPSK modulation transmitter has been implemented in SMIC CMOS 0.13μm technology with a 1.2-V supply voitage and a die size of 0.8×0.95 mm;.This transmitter is based on the impulse response filter method,which uses a tunable R paralleled with a LC frequency selection network to realize continuously adjustable pulse parameters,including bandwidth,width and *** to the extremely low duty of the pulsed UWB,a proposed output buffer is employed to save power consumption ***,measurement results show that the transmitter consumes only 16.3 pJ/pulse to achieve a pulse repetition rate of 100 Mb/*** pulses strictly comply with the FCC spectral *** continuously variable pulse width is from 900 to 1.5 ns and the amplitude with the minimum 178 mVpp and the maximum 432 mVpp can be achieved.

关键词： pulsed UWB generator BPSK RLC

A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

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Journal of Semiconductors 2010年第2期31卷 70-75页

作者：林俪任俊彦叶凡 asic and system state key laboratory Fudan University

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter（ADC） is *** ADC with single track-and-hold（T/H） circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating *** prototype ADC achieves 5.55 bits of the effective number of bits（ENOB） and 47.84 dB of the spurious free dynamic range（SFDR） at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate; it achieves 5.48 bit of ENOB and 43.52 dB of SFDR at 1-MHz input and 4.66 bit of ENOB and 39.56 dB of SFDR at 30.1-MHz input with a 600-MS/s sampling *** ADC has a total power consumption of 25 mW from a 1.4 V supply voltage and occupies 0.17 mm^2 in the 0.13-μm CMOS process.

关键词： analog-to-digital converter cascaded folding active interpolating

Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

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Journal of Semiconductors 2010年第1期31卷 73-78页

作者：马海峰周锋 state key laboratory of asic & system Fudan University

A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.

关键词： low-dropout regulator frequency compensation full on-chip system-on-chip