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A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

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Journal of Semiconductors 2011年第12期32卷 121-127页

作者：郝诗磊梅年松黄煜梅洪志良 State Key laboratory of asic and System Fudan University

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consump- tion at low gain mode. The front-end chip is manufactured on a 0.13-#m CMOS process and occupies an active chip area of 1.2 mm2. It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.

关键词： 5GHz balun LNA capacitive cross-coupling current mode passive mixer current mode switching

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

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Journal of Semiconductors 2009年第6期30卷 100-106页

作者：李娟章华江赵冯洪志良 State Key laboratory of asic & System Fudan University

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are *** calibration and control system,which is adopted to ensure an achievable signal-to-noise ratio and bit error rate,consists of a digitally controlled,high resolution dB-linear automatic gain control（AGC）,an inphase（I） and quadrature（Q） gain and phase mismatch calibration,and an automatic frequency calibration（AFC） of a wideband voltage-controlled oscillator in a PLL based frequency *** calibration system has a low design complexity with little power and small die *** results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB,respectively,which means the image rejection ratio is better than 60 *** addition,the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.

关键词： short range device AGC AFC receiver I/Q calibration

A 16.3 p J/pulse low-complexity and energy-efficient transmitter with adjustable pulse parameters

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Journal of Semiconductors 2011年第6期32卷 119-125页

作者：蒋俊赵裔邵轲陈虎夏伶俐洪志良 State Key laboratory of asic and System Fudan University

This paper presents a novel,fully integrated transmitter for 3-5 GHz pulsed *** BPSK modulation transmitter has been implemented in SMIC CMOS 0.13μm technology with a 1.2-V supply voitage and a die size of 0.8×0.95 mm;.This transmitter is based on the impulse response filter method,which uses a tunable R paralleled with a LC frequency selection network to realize continuously adjustable pulse parameters,including bandwidth,width and *** to the extremely low duty of the pulsed UWB,a proposed output buffer is employed to save power consumption ***,measurement results show that the transmitter consumes only 16.3 pJ/pulse to achieve a pulse repetition rate of 100 Mb/*** pulses strictly comply with the FCC spectral *** continuously variable pulse width is from 900 to 1.5 ns and the amplitude with the minimum 178 mVpp and the maximum 432 mVpp can be achieved.

关键词： pulsed UWB generator BPSK RLC

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

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Journal of Semiconductors 2011年第8期32卷 98-103页

作者：曹圣国杨玉庆谈熙闫娜闵昊 State Key laboratory of asic & System Fudan University

A phase-locked loop（PLL） frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator（VCO） is *** phase-switching prescaler with a novel modulus control mechanism is much more robust on process *** Q factor of the inductor,I-MOS capacitors and varactors in the VCO are *** proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm^*** locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.

关键词： PLL frequency synthesizer differential voltage controlled oscillator phase-switching prescaler CMOS

A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application

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Journal of Semiconductors 2009年第3期30卷 97-103页

作者：李娟赵冯叶国敬洪志良 State Key laboratory of asic & System Fudan University

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier （PA）, frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR （image rejection ratio） so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of-60 dBm and a control gain of 60 dB. The S11 reaches -20 dB at 433 MHz and -10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm^2 including the bias circuit.

关键词： short range device low-power low-cost receiver I/Q imbalance calibration

Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

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Journal of Semiconductors 2010年第1期31卷 73-78页

作者：马海峰周锋 State Key laboratory of asic & System Fudan University

A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.

关键词： low-dropout regulator frequency compensation full on-chip system-on-chip

A 0.18μm CMOS fluorescent detector system for bio-sensing application

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Journal of Semiconductors 2009年第1期30卷 44-49页

作者：刘楠陈国平洪志良 State Key laboratory of asic & System Fudan University

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier （CTIA）, and a 12 bit pipelined analog-to- digital converter （ADC）, and is implemented in a 0.18μm standard CMOS process. Some special techniques, such as a ＂contact imaging＂ detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm^2 and consumes 37 mW.

关键词： fluorescence detecting contact imaging pipelined ADC CTIA pixel dark current

CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

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Journal of Semiconductors 2011年第9期32卷 106-111页

作者：付健梅年松黄煜梅洪志良 asic & System State Key laboratory Fudan University

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is *** transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended *** a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively. The die size is 0.91×1.12 mm;.

关键词： CMOS PA driver on-chip transformer impedance transformation linearity efficiency

A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

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Journal of Semiconductors 2011年第12期32卷 95-100页

作者：谢任重江晨李伟男黄煜梅洪志良 State Key laboratory of asic and System Fudan University

A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.

关键词： analog baseband digital-assisted DCOC reconfigurable receiver