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Journal of semiconductors 2010年第2期31卷 45-48页

作者：李明杨立吾康晋锋王阳元 Institute of Microelectronics Peking University semiconductor Manufacturing International corporation

This paper presents a new circuit scheme to control the current surge in the boosting phase of an radio frequency identification-nonvolative memory *** introducing a circuit block consisting of a current reference and a current mirror,the new circuit scheme can keep the period-average current of the pump constantly below the desired level,for example,2.5μ***,it can prevent the rectified supply of the RFID tag IC from collapsing in the boosting phase of the *** presented scheme could effectively reduce the voltage drop on the rectified supply from more than 50%to even zero,but could cost less ***,an analytical expression to calculate the boosting time of a pump in the new scheme is developed.

关键词： charge pump current surge NVM pump RFID

SOLVING SECOND ORDER DIFFERENTIAL EQUATIONS IN QUANTUM MECHANICS BYORDER REDUCTION

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Acta Mathematica Scientia 2003年第2期23卷 274-288页

作者： C.Ted Chen Grace semiconductor Manufacturing corporation 2nd Floor

Solving the famous Hermite, Legendre, Laguerre and Chebyshev equations requires different techniques of unique character for each equation. By reducing these differential equations of second order to a common solvable differential equation of first order, a simple common solution is provided to cover all the existing standard solutions of these named equations. It is easier than the method of generating functions and more powerful than the Probenius method of power series.

关键词： Second order differential equations quantum mechanics common solution

A high performance 90 nm CMOS SAR ADC with hybrid architecture

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Journal of semiconductors 2010年第1期31卷 51-57页

作者：佟星元陈剑鸣朱樟明杨银堂 Institute of Microelectronics Xidian University Corp DS Semiconductor Manufacturing International Corporation

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

关键词： analog-to-digital converter CMOS integrated circuits level shifters multi-supply SoC high performance

EFI System Performance Reliability Evaluation Based on Degradation Data Distribution

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Chinese Journal of Electronics 2018年第4期27卷 792-798页

作者： CUI Runlong CHEN Tao State Key Laboratory of Engines Tianjin University Freescale semiconductor (China) Electronics corporation

The performance of Electronic fuel injection(EFI) systems has been significantly improved owing to the enhancement of materials and components. Thus,it is very difficult to obtain enough time-to-failure data for a specific time. This raises a big challenge with regard to traditional reliability evaluations of EFI systems since the evaluations lack abundant failure data. To resolve the problem, this paper proposes a new method. By analyzing the working principle and failure mechanism of an EFI system, the extraction method and degradation analysis of the system parameters are first carried out. Then, a temperature stress degradation model of linear regression based on degradation data distribution is presented. Experimental results show that EFI system performance reliability can be effectively evaluated. This can provide a theoretical basis for an overall performance estimation and proactive maintenance of automotive ECUs.

关键词： Electronic fuel injection(EFI) system Degradation data distribution Performance reliability evaluation Characteristic parameter extraction Temperature stress

Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization

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Tsinghua Science and Technology 2007年第6期12卷 741-746页

作者：潘立阳孙磊伍冬陈军许军朱钧 Institute of Microelectronics Tsinghua University semiconductor Manufacture International corporation

A 4 Mb embedded silicon-oxide-nitride-oxide-silicon （SONOS） memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 105 cycles and a data retention time of at least 10 years.

关键词： flash memory silicon-oxide-nitride-oxide-silicon (SONOS) charge distribution endurance retention

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

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Journal of semiconductors 2010年第10期31卷 121-125页

作者：佟星元杨银堂朱樟明盛文芳 Institute of Microelectronics Xidian University Corp D.S. Semiconductor Manufacturing International Corporation

Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.

关键词： analog-to-digital converter SAR touch screen SoC CMOS integrated circuits low power

A Study on Three Dimensional Mask Effect of Attenuated Phase-Shift Mask in Advanced Optical Lithography

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Chinese Journal of Electronics 2020年第4期29卷 648-650页

作者： WU Yuanfang BAO Guangwen DONG Lisong WEI Yayi School of Microelectronics University of Chinese Academy of Sciences (UCAS) semiconductor Manufacturing International corporation (SMIC)

Along with the extension of optical lithography to 28 nm node and beyond, several effects that can be neglected in previous technology nodes become more and more *** of the most striking effects is the 3D mask effect where the mask transmittance and phase are influenced by the mask *** study started with Kirchhoff mask model based experiment of 28 nm node SRAM cell features based on Attenuated Phase-shift mask(***), which were calibrated into Optical proximity correction(OPC) process models.A 28 nm test model was constructed with Kirchhoff mask modeling *** the standard Kirchhoff effects were working on the test wafer, the 3D mask effects were included for the same *** the interactive relations among these mask data were investigated and found to generate as much as 15 nm edge shift *** mask model was then refit including the 3D mask effect and compared with the Kirchhoff mask model in the simulator to better understand the impact of 3D mask effect on patterns.

关键词： 3D mask effect Kirchhoff OPC modeling Edge shift

Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost

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Journal of semiconductors 2009年第7期30卷 80-82页

作者：单毅何军黄文毅 Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Grace semiconductor Manufacturing corporation

A new thyristor is proposed and realized in the foundry＇s 0.18-μm CMOS process for electrostatic dis-charge（ESD） *** extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor（ULVT thyristor） has a trigger voltage as low as 6.7 V and an ESD robustness exceeding 50 mA/μm, which enables effective ESD *** with the traditional medium-voltage-trigger thyristor（MVT thyristor）, the new structure not only has a lower trigger voltage, but can also provide better ESD protection under both positive and negative ESD zapping conditions.

关键词： thyristor electro-static discharge ultra-low-voltage-trigger positive negative

A 10-bit low power SAR A/D converter based on 90 nm CMOS

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Journal of semiconductors 2009年第10期30卷 100-107页

作者：佟星元杨银堂朱樟明肖艳陈剑鸣 Institute of Microelectronics Xidian University IP-2 of D.S.Division Semiconductor Manufacturing International Corporation

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are *** on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and *** challenges and considerations for high speed SAR A/D converters are ***,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS *** DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB *** an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.

关键词： analog-to-digital converter R-C combination CMOS integrated circuits nonlinearity low power