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Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

Computers, Materials & Continua 2022年第8期72卷 3425-3446页

作者： T.G.Sargunam Lim Way Soong C.M.R.Prabhu Ajay Kumar Singh Faculty of Engineering and Technology Multimedia UniversityMelaka75450Malaysia School of Engineering and Computing Manipal International UniversityNilai71800Malaysia Electronics and Communication Engineering Department NIIT UniversityNeemarana301705India

The use of Internet of Things(IoT)applications become dominant in many *** on-chip data processing and computations are also increasing *** battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT *** cache memory designed on Static Random-Access Memory(SRAM)cell with features such as low power,high speed,and process tolerance are highly important for the IoT memory ***,a process tolerant SRAM cell with low power,improved delay and better stability is presented in this research *** proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55%and 47.75%for write and 35.59%and 36.56%for read operations compared to 6 T and 8 T SRAM *** cell shows an improved write delay of 26.46%and 37.16%over 6 T and 8T and read delay is lowered by 50.64%and 72.90%against 6 T and 10 T *** symmetric design used in core latch to improve the write noise margin(WNM)by 17.78%and 6.67%whereas the single ended separate read circuit improves the Read Static Noise Margin(RSNM)by 1.88x and 0.33x compared to 6 T and 8T *** read power delay product and write power delay product are lower by 1.94x,1.39x and 0.17x,2.02x than 6 T and 8 T cells *** lower variability from 5000 samples validates the robustness of the proposed *** simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit(GPDK)45 nm technology file in this work.

关键词： SRAM cell low power process efficient read stability write ability static noise margin PVT variation internet of things

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Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS

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International Journal of Modeling, Simulation, and Scientific Computing 2021年第4期12卷 184-200页

作者： Neha Sharma Rajeevan Chandel Electronics and Communication Engineering National Institute of Technology Hamirpur Hamirpur Himachal PradeshIndia

With technology scaling,stability,power dissipation,and device variability,the impact of process,voltage and temperature(PVT)variations has become dominant for static random access memory(SRAM)analysis for productivity and *** this paper,ten-transistors(10T)and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors(FGMOS).Power centric parameters *** power,write power,hold power and delay are the performance analysis ***,the stochastic parameter variation to study the variability tolerance of the redesigned cell,PVT variations and Monte Carlo simulations have been carried out for 10T FGMOS SRAM *** has been illustrated with the conventional butterfly method giving read static noise margin(RSNM)and write static noise margin(WSNM)metrics for read stability and write ability,respectively.A comparative analysis with standard six-transistor SRAM cell is carried *** simulative analysis has been carried out for 32 nm technology *** redesigned FGMOS SRAM cells provide improved ***,these are robust and reliability efficient with comparable stability.

关键词： Floating gate MOSFETs Monte Carlo analysis process corner analysis SRAM read stability write ability

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