Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

作     者：T.G.Sargunam Lim Way Soong C.M.R.Prabhu Ajay Kumar Singh 

作者机构：Faculty of Engineering and TechnologyMultimedia UniversityMelaka75450Malaysia School of Engineering and ComputingManipal International UniversityNilai71800Malaysia Electronics and Communication Engineering DepartmentNIIT UniversityNeemarana301705India 

出 版 物：《Computers, Materials & Continua》 (计算机、材料和连续体（英文）)

年 卷 期：2022年第72卷第8期

页      面：3425-3446页

核心收录：

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：International Medical University  IMU 

主　　题：SRAM cell low power process efficient read stability write ability static noise margin PVT variation internet of things 

摘      要：The use of Internet of Things(IoT)applications become dominant in many *** on-chip data processing and computations are also increasing *** battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT *** cache memory designed on Static Random-Access Memory(SRAM)cell with features such as low power,high speed,and process tolerance are highly important for the IoT memory ***,a process tolerant SRAM cell with low power,improved delay and better stability is presented in this research *** proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55%and 47.75%for write and 35.59%and 36.56%for read operations compared to 6 T and 8 T SRAM *** cell shows an improved write delay of 26.46%and 37.16%over 6 T and 8T and read delay is lowered by 50.64%and 72.90%against 6 T and 10 T *** symmetric design used in core latch to improve the write noise margin(WNM)by 17.78%and 6.67%whereas the single ended separate read circuit improves the Read Static Noise Margin(RSNM)by 1.88x and 0.33x compared to 6 T and 8T *** read power delay product and write power delay product are lower by 1.94x,1.39x and 0.17x,2.02x than 6 T and 8 T cells *** lower variability from 5000 samples validates the robustness of the proposed *** simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit(GPDK)45 nm technology file in this work.