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Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

Intelligent Automation & Soft Computing 2023年第2期35卷 1767-1781页

作者： C.Arun Prasath C.Gowri Shankar Department of Electronics and Communication Engineering Mahendra Engineering CollegeNamakkal637503India Department of Electrical and Electronics Engineering KSR College of EngineeringTiruchengode637215India

Leakage power and propagation delay are two signiﬁcant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit *** Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage *** is used to reduce stacking leakage as well as total *** Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent *** this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino *** efﬁciency and effec-tiveness of the domino circuit are demonstrated through simulation *** suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of *** proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR *** per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.

关键词： Domino logic power consumption ﬁgure of merit adaptive sub-threshold voltage level wide fan-in gates

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