Adaptive Sub-Threshold Voltage Level Control for Voltage Deviate-Domino Circuits

作     者：C.Arun Prasath C.Gowri Shankar 

作者机构：Department of Electronics and Communication EngineeringMahendra Engineering CollegeNamakkal637503India Department of Electrical and Electronics EngineeringKSR College of EngineeringTiruchengode637215India 

出 版 物：《Intelligent Automation & Soft Computing》 (智能自动化与软计算（英文）)

年 卷 期：2023年第35卷第2期

页      面：1767-1781页

核心收录：

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Domino logic power consumption figure of merit adaptive sub-threshold voltage level wide fan-in gates 

摘      要：Leakage power and propagation delay are two significant issues found in sub-micron technology-based Complementary Metal-Oxide-Semiconductor(CMOS)-based Very Large-Scale Integration(VLSI)circuit *** Channel Metal Oxide Semiconductor(PMOS)has been replaced by Negative Channel Metal Oxide Semiconductor(NMOS)in recent years,with low dimen-sion-switching changes in order to shape the mirror of voltage *** is used to reduce stacking leakage as well as total *** Logic Cir-cuit is a powerful and versatile digital programmer that gained popularity in recent *** this study regarding Adaptive Sub Threshold Voltage Level Control Pro-blem,the researchers intend to solve the contention issues,reduce power dissipa-tion,and increase the noise immunity by proposing Adaptive Sub Threshold Voltage Level Control(ASVLC)-based domino *** efficiency and effec-tiveness of the domino circuit are demonstrated through simulation *** suggested system makes use of high-speed broad fan-gate circuits,occupies mini-mum space,and consumes meagre amount of *** proposed circuit was validated in Cadence simulation tool at a supply voltage of 1V,frequency of 100 MHz,and an operating temperature of 27°C with 64 input OR *** per the simulation results,the suggested Domino Gate reduced the power dissipa-tion by 17.58 percent and improved the noise immunity by 1.21 times in compar-ison with standard domino logic circuits.