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A novel 2.95–3.65 GHz CMOS LC-VCO using tuning curve compensation

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Journal of Semiconductors 2009年第10期30卷 63-67页

作者：肖时茂马成炎叶甜春 Institute of Microelectronics Chinese Academy of Sciences Hangzhou Zhongke Microelectronics Co.Ltd

This paper presents a new CMOS LC-VCO with a 2.95–3.65 GHz tuning *** large tuning range is achieved by tuning curve compensation using a novel varactor configuration,which is mainly composed of four accumulation-mode MOS varactors（A-MOS）and two bias *** proposed varactor has the advantages of optimizing quality factor and tuning range simultaneously,linearizing the effective capacitance and thus greatly reducing the amplitude-to-phase modulation（AM-PM）*** circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS *** phase noise is lower than–91 dBc at 100 kHz offset from a 3.15 GHz carrier while measured tuning range is 21.5%as the control voltage varies from 0 to 1.8 *** VCO including buffers consumes 2.8 mA current from a 1.8 V supply.

关键词： CMOS A-MOS voltage-controlled oscillator tuning curve compensation

Design of a 4.6 GHz high-performance quadrature CMOS VCO using transformer couple

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Journal of Semiconductors 2009年第2期30卷 61-64页

作者：吴秀山王志功李智群李青 Institute of RF- & OE-ICs Southeast University College of Electrical & Mechanical Engineering China Jiliang University

A CMOS quadrature LC-tank voltage-controlled oscillator topology which uses a planar spiral transformer as coupling elements has been implemented in mixed-signal and RF 1P6M 0.18μm CMOS technology of SMIC. The measured phase noise is -125.7 dBc/Hz at an offset frequency of 1 MHz from the carrier of 4.6 GHz while the VCO core circuit draws only of 10 mW from a 1.8 V supply. The measured phase error is approximately 1.5° based on the time domain outputs and the output power is about -2 dBm. The VCO can cover the frequency range of 4.36-4.68 GHz. The tuning range is 320 MHz （7.0%） and the FOM is -189 dB.

关键词： low-phase-noise transformer quadrature voltage-controlled oscillator couple

A 2.5-Gb/s fully-integrated,low-power clock and recovery circuit in 0.18-μm CMOS

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Journal of Semiconductors 2010年第3期31卷 101-106页

作者：张长春王志功施思郭宇峰 Institute of RF-& OE-ICs Southeast University

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery （CDR） circuit has been designed and fabricated in SMIC＇s 0.18-μm CMOS technology. The Pottbiicker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440μm2, and consumes a power of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV. It has a pull-in range of 800 MHz, and a phase noise of-111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.

关键词： clock and data recovery phase frequency detector voltage-controlled oscillator bang-bang jitter

Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

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Journal of Semiconductors 2010年第8期31卷 137-140页

作者：吴秀山王志功李智群夏峻李青 College of Electrical & Mechanical Engineering China Jiliang University Institute of RF-& OE-ICs Southeast University Key Laboratory of ASIC Design of Jiangsu Province Nantong University

A fully integrated cross-coupled LC tank voltage-controlled oscillator（LC-VCO） using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is-125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz,while the VCO core circuit draws only 640μW from a 0.4-V *** designed VCO can cover a frequency range from 2.28 to 2.48 *** tuning range of the circuit is 200 MHz（8.7%） and the FOM is-195.7 dB,which is suitable for an IEEE 802.11b receiver.

关键词： low phase noise low-power transformer voltage-controlled oscillator feedback

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

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Journal of Semiconductors 2011年第7期32卷 108-114页

作者：李振荣庄奕琪李兵靳刚 Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices School of MicroelectronicsXidian University

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature（I/Q） local oscillating signal.A high-speed 8/9 dual-modulus prescaler（DMP）,a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power *** total area of the receiver is 2.4×1.6 mm^2.

关键词： Beidou receiver frequency synthesizer voltage-controlled oscillator quadrature output divider phase noise

A low power wide-band CMOS PLL frequency synthesizer for portable hybrid GNSS receiver

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Journal of Semiconductors 2010年第3期31卷 85-89页

作者：肖时茂于云丰马成炎叶甜春殷明 Institute of Microelectronics Chinese Academy of Sciences Hangzhou Zhongke Microelectronics Co Ltd

The design consideration and implementation of a CMOS frequency synthesizer for the portable hybrid global navigation satellite system are presented. The large tuning range is achieved by tuning curve compensation using an improved VCO resonant tank, which reduces the power consumption and obtains better phase noise performance. The circuit is validated by simulations and fabricated in a standard 0.18 μm 1P6M CMOS process. Close-loop phase noise measured is lower than -95 dBc at 200 kHz offset while the measured ttming range is 21.5% from 1.47 to 1.83 GHz. The proposed synthesizer including source coupled logic prescaler consumes 6.2 mA current from 1.8 V supply. The whole silicon required is only 0.53 mm2.

关键词： CMOS GNSS dual-modulus voltage-controlled oscillator frequency synthesizer

5-Gb/s 0.18-μm CMOS 2:1 multiplexer with integrated clock extraction

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Journal of Semiconductors 2009年第9期30卷 96-101页

作者：张长春王志功施思苗澎田玲 Institute of RF- & OE-ICs Southeast University School of Science and Engineering Southeast University

A 5-Gb/s 2 ： 1 MUX （multiplexer） with an on-chip integrated clock extraction circuit which possesses the function of automatic phase alignment （APA）, has been designed and fabricated in SMIC＇s 0.18 μm CMOS technology. The chip area is 670 × 780 μm^2. At a single supply voltage of 1.8 V, the total power consumption is 112 mW with an input sensitivity of less than 50 mV and an output single-ended swing of above 300 mV. The measurement results show that the IC can work reliably at any input data rate between 1.8 and 2.6 Gb/s with no need for external components, reference clock, or phase alignment between data and clock. It can be used in a parallel optic-fiber data interconnecting system.

关键词： multiplexer clock extraction automatic phase alignment phase frequency detector voltage-controlled oscillator

A low-power current self-adjusted VCO using a bottom PMOS current source

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Journal of Semiconductors 2014年第9期35卷 126-130页

作者：盛志雄于峰崎 Department of Integrated Electronics Shenzhen Institutes of Advanced Technology Chinese Academy of Sciences Institute of Microelectronics Chinese Academy of Sciences The Chinese University of Hong Kong University of Chinese Academy of Sciences

This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency （high Cvar） can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of 〈1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is-104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.

关键词： low-power phase-noise quality factor current self-adjusted technique voltage-controlled oscillator

A wide-band low phase noise LC-tuned VCO with constant K_(VCO)/ω_(osc) for LTE PLL

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Journal of Semiconductors 2012年第2期33卷 106-110页

作者： Huang Jiwei Wang Zhigong Li Kuili Li Zhengping Wang Yongping College of Physics and Information Engineering Fuzhou UniversityFuzhou 350002China Institute of RF&OE-IC Southeast UniversityNanjing 210096China Guangzhou Runxin Information Technology Ltd.Co. Guangzhou 510663China

A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is *** order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or *** switches are controlled by switching *** this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is *** 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS *** VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.

关键词： voltage-controlled oscillator loop bandwidth LTE Kvco low phase noise