A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

作     者：李振荣 庄奕琪 李兵 靳刚 

作者机构：Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and DevicesSchool of MicroelectronicsXidian University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2011年第32卷第7期

页      面：108-114页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：Beidou receiver frequency synthesizer voltage-controlled oscillator quadrature output divider phase noise 

摘      要：A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature（I/Q） local oscillating signal.A high-speed 8/9 dual-modulus prescaler（DMP）,a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power *** total area of the receiver is 2.4×1.6 mm^2.