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Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

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Chinese Physics B 2010年第5期19卷 524-529页

作者：胡爱斌徐秋霞 Institute of Microelectronics Chinese Academy of Sciences

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors （p-MOSFETs） with hafnium silicon oxynitride （HfSiON） gate dielectric and tantalum nitride （TAN） metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor （MOS） capacitors may be caused by charge trapping centres in GeOx （1 〈 x 〈 2）. Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/（V.s） and 81.0 cm2/（V.s）, respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

关键词： Ge substrate transistor HfSiON hole mobility

Remembering John Bardeen: inventor of transistor

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Journal of Semiconductors 2019年第2期40卷 9-10页

作者： M.A.Rafiq Chuanbo Li Buwen Cheng Department of Physics and Applied Mathematics Pakistan Institute of Engineering and Applied Sciences (PIEAS) State Key Laboratory on Integrated optoelectronics Institute of Semiconductors Chinese Academy of Sciences School of Science Minzu University of China

transistor's invention revolutionized global society by spawning electronics industry. John Bardeen is among one of the inventors of transistor. He was a genius and one of the most influential semiconductor Physicist ... 详细信息

关键词： Remembering John Bardeen inventor of transistor

Polarity control of carrier injection for nanowire feedback field-effect transistors

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Nano Research 2019年第10期12卷 2509-2514页

作者： Doohyeok Lim Sangsig Kim Department of Electrical Engineering Korea University145 Anam-roSeongbuk-guSeoul 02841Republic of Korea

We present polarity control of the carrier injection for a feedback field-effect transistor(FBFET)with a selectively thinned p^+-i-n^+Si nanowire(SiNW)channel and two separate gates.The SiNW FBFET can be reconfigured in the p-or n-channel operation modes via simple control of electric signals.The two separate gates induce potential barriers in the SiNW channel for selective control of the carrier injection.In contrast to previously reported rec on figurable tran sistors,our tran sistor features symmetry of the electrical characteristics for the p-and n-cha nnel operation modes.Positive-feedback operation of the SiNW FBFET provides superior switching characteristics for the p-and n-type 8nfigurations,including the on/off ratios(~10^5)and subthreshold swings(1.36-1.78 mV/dec).This novel tran sistor is a promising can didate for reconfigurable electro nics.

关键词： silicon nanowire reconfigurable transistor positive-feedback loop separate gate

Efficient passivation of monolayer MoS2 by epitaxially grown 2D organic crystals

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Science Bulletin 2019年第22期64卷 1700-1706页

作者： Xin Xu Zefeng Chen Beilei Sun Yu Zhao Li Tao Jian-Bin Xu Department of Electronic Engineering The Chinese University of Hong KongHong KongChina Guangdong Provincial Key Laboratory of Functional Soft Condensed Matter School of Material and EnergyGuangdong University of TechnologyGuangzhou 510006China

Monolayer molybdenum disulfide(Mo S2)is considered to be a promising candidate for field-effect transistors and photodetectors due to its direct bandgap and atomically thin properties.However,the Mo S2devices are impeded by the intrinsic surface defects and environmental adsorption such as H2O and O2.Here,we demonstrated a highly ordered,ultrathin(<5 nm)and scalable N,N0-ditridecylperylene-3,4,9,10-tetracarboxylic diimide(PTCDI-C13)passivation layer that can be epitaxially grown on Mo S2.The van der Waals interface between PTCDI-C13 and Mo S2can efficiently reduce the surface traps and isolate Mo S2from ambient.As a result,the passivated devices exhibit huge improvement in both carrier mobility(from 0.5 to 8.3 cm^2/(V s))and sub-threshold swing(from 16.7 to 1.6 V/dec).Also,the photodetector made on Mo S2after passivation has a much faster response speed(from 3 s to 10 ms)without significant sacrifice of the responsivity.Our method provides a facile approach to realize high-performance two-dimensional electronic and optoelectronic devices.

关键词： Molybdenum disulfide Filed-effect transistor Photodetector Passivation

Dimethylacetamide-promoted Direct Arylation Polycondensation of 6,6’-Dibromo-7,7’-diazaisoindigo and(E)-1,2-bis(3,4-difluorothien-2-yl)ethene toward High Molecular Weight n-Type Conjugated Polymers

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Chinese Journal of Polymer Science 2019年第11期37卷 1099-1104页

作者： Kai Guo Yu Jiang Ying Sui Yun-Feng Deng Yan-Hou Geng School of Materials Science and Engineering Tianjin University Tianjin 300072 China State Key Laboratory of Polymer Physics and Chemistry Changchun Institute of Applied Chemistry Chinese Academy of Sciences Changchun 130022 China Tianjin Key Laboratory of Molecular Optoelectronic Science Tianjin University and Collaborative Innovation Center of Chemical Science and Engineering (Tianjin) Tianjin 300072 China

A highly efficient and eco-friendly protocol for the synthesis of an alternating copolymer poly(7,7'-diazaisoindigo-alt-(E)-1,2- bis(3,4-difluorothien-2-yl)ethene)(PAIID-4FTVT) via direct arylation polycondensation (DArP) is presented. Through detailed study, we found that the inhibitory effect of 7,7'-diazaisoindigo on DArP stemmed from the coordination of N atom with catalyst can be overcome by using dimethylacetamide (DMAc) as the co-solvent. Thus, PAIID-4FTVT with number-average molecular weight (Mn)>100kDa was synthesized via DArP by optimizing the content of DMAc. Matrix-assisted laser desorption ionization time-of-flight (MALDI-TOF) mass spectroscopy revealed that PAIID-4FTVT was defect-free. Top gate and bottom contact (TG/BC) organic thin-film transistors (OTFTs) were fabricated to characterize the semiconducting properties of the polymers. PAIID-4FTVT displayed unipolar n-type characteristics with the electron mobility (μe) strongly dependent on Mn. The highest μe up to 0.25 cm^2·V^-1 s^-1 was achieved with the high molecular weight sample.

关键词： Direct arylation polycondensation Conjugated polymer 7,7-Diazaisoindigo Organic thin-film transistor Electron mobility

Trap and 1/f-noise effects at the surface and core of GaN nanowire gateall-around FET structure

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Nano Research 2019年第4期12卷 809-814页

作者： Mallem Siva Pratap Reddy Ki-Sik Im Jung-Hee Lee Raphael Caulmione Sorin Cristoloveanu School of Electronics Engineering Kyungpook National University Daegu 41566 Republic of Korea Advanced Material Research Center Kumoh National Institute of Technology Gumi 39177 Republic of Korea SOITEC Bernin 38190 France Institute of Microelectronics Electromagnetism and Photonics Grenoble Polytechnic Institute Minatec Grenoble 38016 France

Using capacitance,conductance and noise measurements,we investigate the trapping behavior at the surface and in the core of triangular-shaped one-dimensional (1 D) array of GaN nanowire gate-all-around field effect transistor (GAA FET),fabricated via a top-down process.The surface traps in such a low dimensional device play a crucial role in determining the device performance.The estimated surface trap density rapidly decreases with increasing frequency,ranging from 6.07 × 1012 cm-2·eV-1 at 1 kHz to 1.90 × 1011 cm-2·eV-1 at 1 MHz,respectively.The noise results reveal that the power spectral density increases with gate voltage and clearly exhibits 1/f-noise signature in the accumulation region (Vgs > Vth =3.4 V) for all frquencies.In the surface depletion region (1.5 V < Vgs < Vth),the device is governed by 1/fat lower frequencies and 1/f2 noise at frequencies higher than ~ 5 kHz.The 1/f2 noise characteristics is attributed to additional generation-recombination (G-R),mostly caused by the electron trapping/detrapping process through deep traps located in the surface depletion region of the nanowire.The cutoff frequency for the 1/f2 noise characteristics further shifts to lower frequency of 102-103 Hz when the device operates in deep-subthreshold region (Vgs < 1.5 V).In this regime,the electron trapping/detrapping process through deep traps expands into the totally depleted nanowire core and the G-R noise prevails in the entire nanowire channel.

关键词： gate-all-around field effect transistor (FET) nanowire GaN trap 1/f-noise

In situ fabrication of organic electrochemical transistors on a microfluidic chip

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Nano Research 2019年第8期12卷 1943-1951页

作者： Jianlong Ji Mangmang Li Zhaowei Chen Hongwang Wang Xiaoning Jiang Kai Zhuo Ying Liu Xing Yang Zhen Gu Shengbo Sang Yang Shu College of Information and Computer Taiyuan University of TechnologyTaiyuan 030024China Department of Mechanical and Aerospace Engineering North Carolina State University Raleigh 27695USA Department of Bioengineering California Nanosystems Institute University of CaliforniaLos AngelesLos Angeles 90095USA The State Key Laboratory of Precision Measurement Technology and Instruments Department of Precision InstrumentTsinghua UniversityBeijing 100084China Department of Chemistry Colleges of SciencesNortheastern UniversityShenyang 110819China

Microfluid chips integrating with organic electrochemical transistors (OECTs) are useful for manufacturing biosensors with high throughput and large-scale analyses. We report here the utilization of alternating current (AC) electrodeposition to fabricate OECTs in situ on a microfiuid chip. With this method, the organic semiconductor (OS) layer with a channel length of 8μm was readily prepared without requiring the postbonding process in the conventional construction of microfluidic chips. Poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate)/graphene quantum dots (PEDOT:PSS/GQDs) composites with different morphologies, such as microfilms, nanodendrites and nanowires were electropolymerized. The mass transfer process of the electropolymerization reaction was evidenced to be diffusion limited. Morphologies, growth directions, and chemical structures of OS layers could be tuned by the amplitude and the frequency of the AC voltage. Transfer and output characteristic curves of OECTs were measured on the microfluidic chip. The maximum transconductance, on/off current ratio and threshold voltage measured in the experiment was 1.58 mS, 246, and 0.120 V, respectively.

关键词： electrodeposition in situ microfluidic chip PEDOT:PSS/GQDs composite transistor

Quasi-two-dimensionalβ-Ga2O3 field effect transistors with large drain current density and low contact resistance via controlled formation of interfacial oxygen vacancies

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Nano Research 2019年第1期12卷 143-148页

作者： Zhen Li Yihang Liu Anyi Zhang Qingzhou Liu Chenfei Shen Fanqi Wu Chi Xu Mingrui Chen Hongyu Fu Chongwu Zhou Ming Hsieh Department of Electrical Engineering Mork Family Department of Chemical Engineering and Material ScienceDepartment of Physics and AstronomyUniversity of Southern CalifomiOy Los AngelesCalifornia 90089USA

Quasi-two-dimensi on al(2D)β-Ga2O3 is a rediscovered metal-oxide semiconductor with an ultra-wide bandgap of 4.6-4.9eV.It has been reported to be a promising material for next-generation power and radio frequency electronics.Field effect transistors(FETs)that can switch at high voltage are key compone nts in power and radio frequency devices,and reliable Ohmic con tacts are essential for high FET performance.However,obtaining low contact resistance onβ-Ga2O3 FETs is difficult since reactions betweenβ-Ga2O3 and metal contacts are not fully understood.Herein,we experimentally demonstrate the importanee of reactions at the metal/β-Ga2O3 interface and the corresponding effects of these reactions on FET performance.When Ti is employed as the metal contact,annealing ofβ-Ga2O3 FETs in argon can effectively transform Schottky contacts into Ohmic contacts and permit a large drain current density of-3.1 mA//μm.The contact resistance(Rcontact)between the Ti electrodes andβ-Ga2O3 decreased from^430 to^0.387Ω·mm after annealing.X-ray photoelectron spectroscopy(XPS)confirmed the formation of oxygen vacancies at the Ti/β-Ga2O3 interface after annealing,which is believed to cause the improved FET performance.The results of this study pave the way for greater application ofβ-Ga2O3 in electronics.

关键词： quasi-two-dimensional material metal-oxides field effect transistor β-Ga2O3 contact resistanee

The origin of gate bias stress instability and hysteresis in monolayer WS2 transistors

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Nano Research 2020年第12期13卷 3278-3285页

作者： Changyong Lan Xiaolin Kang You Meng Renjie Wei Xiuming Bu SenPo Yip Johnny C.Ho State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of ChinaChengdu610054China School of Optoelectronic Science and Engineering University of Electronic Science and Technology of ChinaChengdu610054China Department of Materials Science and Engineering City University of Hong KongKowloonHong Kong999077China State Key Laboratory of Terahertz and Millimeter Waves City University of Hong KongKowloonHong Kong999077China Key Laboratory of Advanced Materials Processing&Mold of Ministry of Education Zhengzhou UniversityZhengzhou450002China

Due to the ultra-thin nature and moderate carrier mobility,semiconducting two-dimensional(2D)materials have attracted extensive attention for next-generation electronics.However,the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications.Herein,the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully.The transistor performance is found to be strongly affected by the gate bias stress time,sweeping rate and range,and temperature.Based on the systematical study and complementary analysis,charge trapping is determined to be the major contribution for these observed phenomena.Importantly,due to these charge trapping effects,the channel current is observed to decrease with time;hence,a rate equation,considering the charge trapping and time decay effect of current,is proposed and developed to model the phenomena with excellent consistency with experimental data.All these results do not only indicate the validity of the charge trapping model,but also confirm the hysteresis being indeed caused by charge trapping.Evidently,this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors,which can be also applicable to other kinds of transistors.

关键词： charge trapping gate bias stress instability hysteresis WS2 transistor