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A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

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Chinese Physics B 2012年第5期21卷 596-601页

作者：马飞刘红侠匡潜玮樊继斌 Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Material and Devices School of MicroelectronicsXidian University

We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric *** model can predict the fringing-induced barrier lowering effect and the short channel *** is also valid for non-LDD *** on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is *** with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric *** model is verified at the end of the paper.

关键词： threshold voltage high-k gate dielectric fringing-induced barrier lowering short channeleffect

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO_2 /Si stacked MOSFETs

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Chinese Physics B 2012年第10期21卷 439-445页

作者：马飞刘红侠樊继斌王树龙 Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Material and Devices School of MicroelectronicsXidian University

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are *** flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function *** two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary *** model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.

关键词： metal-gate high-k work function flat-band voltage threshold voltage metal-oxide-semiconductor field-effect transistor

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

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Chinese Physics B 2014年第11期23卷 620-625页

作者： Shweta Tripathi Department of Electronics & Communication Engineering Motilal Nehru National Institute of Technology

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

关键词： dual-material-gate MOSFET lightly doped drain short channel effect threshold voltage

A threshold voltage and drain current model for symmetric dual-gate amorphous In GaZnO thin film transistors

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Science China(Information Sciences) 2018年第2期61卷 194-203页

作者： Minxi CAI Ruohe YAO School of Electronic and Information Engineering South China University of Technology

Based on the drift-diffusion theory, a simple threshold voltage and drain current model for symmetric dual-gate(DG) amorphous In Ga Zn O(a-IGZO) thin film transistors(TFTs) is developed. In the subthreshold region, most of the free electrons are captured by trap states in the bandgap of a-IGZO, thus the ionized trap states are the main contributor to the diffusion component of device drain current. Whereas in the above-threshold region, most of the trap states are ionized, and free electrons increase dramatically with gate voltage, which in turn become the main source of the drift component of device drain current. Therefore,threshold voltage of DG a-IGZO TFTs is defined as the gate voltage where the diffusion component of drain current equals the drift one, which can be determined with physical parameters of a-IGZO. The developed threshold voltage model is proved to be consistent with trap-limited conduction mechanism prevailing in a-IGZO, with the effect of drain bias being also taken into account. The gate overdrive voltage-dependent mobility is well modeled by the derived threshold voltage, and comparisons of the obtained drain current with experiment data show good verification of our model.

关键词： amorphous In Ga Zn O drift-diffusion current dual-gate thin film transistors threshold voltage

An analytical threshold voltage model for dual-strained channel PMOSFET

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Chinese Physics B 2010年第11期19卷 608-614页

作者：秦珊珊张鹤鸣胡辉勇戴显英宣荣喜舒斌 Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices School of MicroelectronicsXidian University

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey（s-Si/s-SiGe/Si1-yGey） metal-oxide-semiconductor field-effect transistor （PMOSFET）, analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel （compressive strained SiGe） than in the surface channel （tensile strained Si）, because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor （MOSFET） designs.

关键词： strained Si strained SiGe dual-channel metal-oxide-semiconductor field-effect transistor (MOSFET) threshold voltage

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

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Chinese Physics B 2016年第10期25卷 518-524页

作者： Shweta Tripathi Department of Electronics & Communication Engineering Motilal Nehru National Institute of Technology

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

关键词： triple material symmetrical gate stack(TMGS) DG MOSFET gate stack short channel effect drain induced barrier lowering threshold voltage

Directly extracting both threshold voltage and series resistance from the conductance-voltage curve of an AlGaN/GaN Schottky diode

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Chinese Physics B 2013年第7期22卷 426-429页

作者：吕元杰冯志红顾国栋敦少博尹甲运韩婷婷盛百城蔡树军刘波林兆军 Science and Technology on Application Specific Integrated Circuit (ASIC) Laboratory Hebei Semiconductor Research Institute School of Physics Shandong University

An Ni/Au Schottky contact on an AlGaN/GaN heterostructure has been prepared. By using the peak-conductance model, the threshold voltage and the series resistance of the AlGaN/GaN diode are simultaneously extracted from the conductance-voltage （G-V） curve and found to be in good agreement with the ones obtained by using the capacitance-voltage （C-V） curve integration and the plot of dV/d（ln I） versus current I. Thus, a method of directly and simultaneously extracting both the threshold voltage and the series resistance from the conductance-voltage curve for the AlGaN/GaN Schottky diode is developed.

关键词： AlGaN/GaN heterostructure Schottky diode threshold voltage series resistance

A physical-based pMOSFETs threshold voltage model including the STI stress effect

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Journal of Semiconductors 2011年第5期32卷 57-61页

作者：吴畏杜刚刘晓彦孙雷康晋峰韩汝琦 Institute of Microelectronics Peking University

The physical threshold voltage model of pMOSFETs under shallow trench isolation （STI） stress has been developed. The model is verified by 130 nm technology layout dependent measurement data. The comparison between pMOSFET and nMOSFET model simulations due to STI stress was conducted to show that STI stress induced less threshold voltage shift and more mobility shift for the pMOSFET. The circuit simulations of a nine stage ring oscillator with and without STI stress proved about 11% improvement of average delay time. This indicates the importance of STI stress consideration in circuit design.

关键词： STI stress threshold voltage mobility strain

Low threshold voltage light-emitting diode in silicon-based standard CMOS technology

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Chinese Optics Letters 2011年第8期9卷 75-78页

作者：董赞王伟黄北举张旭关宁陈弘达 State Key Laboratory on Integrated Optoelectronics Institute of SemiconductorsChinese Academy of Sciences

Low-voltage silicon （Si）-based light-emitting diode （LED） is designed based on the former research of LED in Si-based standard complementary metal oxide semiconductor （CMOS） technology. The low-voltage LED is designed under the research of cross-finger structure LEDs and sophisticated structure enhanced LEDs for high efficiency and stable light source of monolithic chip integration. The device size of low-voltage LED is 45.85x38.4 （#m）, threshold voltage is 2.2 V in common condition, and temperature is 27 ~C. The external quantum efficiency is about 10-6 at stable operating state of 5 V and 177 mA.

关键词： CMOS integrated circuits Light emission Light sources Metallic compounds MOS devices Quantum theory Semiconducting silicon Semiconducting silicon compounds Semiconductor diodes threshold voltage