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A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

作     者:Shweta Tripathi 

作者机构:Department of Electronics & Communication EngineeringMotilal Nehru National Institute of Technology 

出 版 物:《Chinese Physics B》 (中国物理B(英文版))

年 卷 期:2014年第23卷第11期

页      面:620-625页

核心收录:

学科分类:080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术(可授工学、理学学位)] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程(可授工学、理学学位)] 080502[工学-材料学] 0704[理学-天文学] 

主  题:dual-material-gate MOSFET lightly doped drain short channel effect threshold voltage 

摘      要:An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain (DMG-LDD) metal-oxide-semiconductor field-effect transistor (MOSFET) is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects (SCEs) and the drain induced barrier lowering (DIBL) more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

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