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Effects of taping on grinding quality of silicon wafers in backgrinding

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Frontiers of Mechanical Engineering 2021年第3期16卷 559-569页

作者： Zhigang DONG Qian ZHANG Renke KANG Shang GAO Haijun LIU Key Laboratory for Precision and Non-traditional Machining Technology of Ministry of Education Dalian University of TechnologyDalian 116024China CIMS Institute School of Mechanical EngineeringHefei University of TechnologyHefei 230009China

Taping is often used to protect patterned wafers and reduce fragmentation during backgrinding of silicon *** experiments using coarse and fine resinbond diamond grinding wheels were performed on silicon wafers with tapes of different thicknesses to investigate the effects of taping on peak-to-valley(PV),surface roughness,and subsurface damage of silicon wafers after *** showed that taping in backgrinding could provide effective protection for ground wafers from ***,the PV value,surface roughness,and subsurface damage of silicon wafers with taping deteriorated compared with those without taping although the deterioration extents were very *** PV value of silicon wafers with taping decreased with increasing mesh size of the grinding wheel and the final *** surface roughness and subsurface damage of silicon wafers with taping decreased with increasing mesh size of grinding wheel but was not affected by removal *** hope the experimental finding could help fully understand the role of taping in backgrinding.

关键词： taping silicon wafer backgrinding subsurface damage surface roughness

Surface Damage in Wire cut silicon wafers

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Rare Metals 1999年第4期18卷 315-318页

作者：樊瑞新阙端麟浙江大学硅材料科学国家重点实验室浙江杭州 310027 浙江大学硅材料科学国家重点实验室浙江杭州

The surface damage and the damage depth in wire-cut silicon wafers and inner-diameter (ID) cut silicon wafers were studied by means of thickness meter, scanning electron microscopy (SEM) and double crystal X-ray diffractometer. The results show that the surface of wire-cut silicon wafers is rougher than that of ID-cut silicon wafers and the surface damage in wire-cut silicon wafers is more serious than that in ID-cut silicon wafers, while the damage depth in wire-cut silicon wafers is smaller than that in ID-cut silicon wafers. The possible reasons for the generation of surface damage in wire-cut silicon wafers were also discussed.

关键词： wire-cut surface damage silicon wafer

Sensitivity analysis of the surface integrity of monocrystalline silicon to grinding speed with same grain depth-of-cut

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Advances in Manufacturing 2020年第1期8卷 97-106页

作者： Ping Zhou Zi-Guang Wang Ying Yan Ning Huang Ren-Ke Kang Dong-Ming Guo Key Laboratory for Precision and Non-traditional Machining Technology of Ministry of Education.Dalian University of Technology Dalian 116024LiaoningPeople's Republic of China

Mechanisms for removal of materials during the grinding process of monocrystalline silicon have been extensively studied in the past several ***,debates over whether the cutting speed significantly affects the surface integrity are *** address this debate,this study comprehensively investigates the effects of cutting speed on surface roughness,subsurface damage,residual stress,and grinding force for a constant grain *** results illustrate that the changes in the surface roughness and subsurface damage relative to the grinding speed are less obvious when the material is removed in ductile-mode as opposed to in the brittle-ductile mixed mode.A notable finding is that there is no positive correlation between grinding force and surface *** results of this study could be useful for further investigations on fundamental and technical analysis of the precision grinding of brittle materials.

关键词： Rotational grinding silicon wafer Surface integrity Cutting speed Residual stress

Study into grinding force in back grinding of wafer with outer rim

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Advances in Manufacturing 2020年第3期8卷 361-368页

作者： Xiang-Long Zhu Yu Li Zhi-Gang Dong Ren-Ke Kang Shang Gao Key Laboratory for Precision and Non-traditional Machining Technology of Ministry of Education Dalian University of TechnologyDalian116024People’s Republic of China

Back grinding of wafer with outer rim(BGWOR)is a new method for carrier-less thinning of silicon *** present,the effects of process parameters on the grinding force remain ***,a BGWOR normal grinding force model based on grain depth-of-cut was established,and the relationship between grinding parameters(wheel infeed rate,wheel rotational speed,and chuck rotational speed)and normal grinding force was ***,a series of experiments were performed to verify the BGWOR normal grinding force *** study proves that the BGWOR normal grinding force is related to the rotational direction of the wheel and chuck,and the effect of grinding mark density on the BGWOR normal grinding force cannot be ***,this study provides methods for reducing the grinding force and optimizing the back thinning process of the silicon wafer.

关键词： silicon wafer Back grinding of wafer with outer rim(BGWOR) Grinding force Grinding mark density

Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

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Journal of Semiconductors 2011年第10期32卷 78-85页

作者：朱祥龙康仁科董志刚冯光 Key Laboratory for Precision & Non-traditional Machining Technology of Ministry of Education Dalian University of Technology

Double-spindle triple-workstation（DSTW） ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter（≥300 mm） silicon wafers for integrated *** is important, but insufficiently studied,to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work *** this paper,the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed.A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are *** on the proposed configuration,an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are *** proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

关键词： grinder silicon wafer surface shape control chuck dressing modeling

Anomalous Emission And Carrier Effect of Fresh Porous silicon

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Chemical Research in Chinese Universities 2002年第3期18卷 270-273页

作者： ZOU Bing-suo WU Zhen yu CAO Li DAI Jian-hua XIE Si-shen WANG Jian ping Mostafa AEl-Sayed Optical Lab Institute of PhysicsChinese Academy of SciencesBeijing 100080P.R.China Laser Dynamics Laboratory School of Chemistry and BiochemistryGeorgia Institute of TechnologyAtlantaGA30332-0400

The emission and Fourier transformation infrared spectra of freshly prepared porous silicon(PS) and the silicon wafer were examined. Increasing temperature generally led to a decrease in the emission intensities of the PS samples, however, the freshly prepared sample showed an unusually large and sudden increase in its emission intensity at the specific temperature at which the hydrogen ion conductivity in the silicon wafer increased. The O-H vibrations of the silicon wafer also showed a sudden decrease at the same temperature. These results are consistent with the assumption that the luminescence of fresh PS comes from the carrier bound exciton in its confined nanostructure.

关键词： Porous silicon silicon wafer Carrier effect

Finite Element Analysis for Grinding and Lapping of Wire-sawn silicon wafers

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Finite Element Analysis for Grinding and Lapping of Wire-saw...

Finite Element Analysis for Grinding and Lapping of Wire-sawn silicon wafers

第十届国际制造工程与管理会议

作者： Wenjie LIU Z J PEI X J XIN(1. Department of Mechanical and Nuclear Engineering Kansas State University 2. Department of Industrial and Manufacturing Systems Engineering Kansas State University USA)

＜正＞ silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure on silicon wafer manufacturers to develop cost-effective manufacturing processes. A critical issue in wafer production is the waviness induced by wire sawing. If this waviness is not removed, it will affect wafer flatness and semiconductor performance. In practice, both lapping and grinding have been used to flatten wire-sawn wafers. Although grinding is not as effective as lapping in removing waviness, it has many other advantages over lapping （such as higher throughput, fully automatic, and more benign to environment） and has great potential to reduce manufacturing cost of silicon wafers. This paper presents a finite element analysis （FEA） study on grinding and lapping of wire-sawn silicon wafers. An FEA model is first developed to simulate the waviness deformation of wire-sawn wafers in grinding and lapping processes. It is then used to explain how the waviness is removed or reduced by lapping and grinding and why the effectiveness of grinding in removing waviness is different from that of lapping. Furthermore, the model is used to study the effects of various parameters including active-grinding-zone orientation, grinding force, waviness wavelength, and waviness height on the reduction and elimination of waviness. Finally, the results of pilot experiments to verify the model are discussed.

关键词： finite element analysis grinding lapping silicon wafer waviness removal

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厦门大学学报（自然科学版） 2002年第S1期41卷 10-页

作者： Z J PEI X J XIN Department of Industrial and Manufacturing Systems Engineering Kansas State UniversityDepartment of Mechanical and Nuclear Engineering Kansas State University USA

silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure on silicon wafer manufacturers to develop cost-effective manufacturing processes. A critical issue in wafer production is the waviness induced by wire sawing. If this waviness is not removed, it will affect wafer flatness and semiconductor performance. In practice, both lapping and grinding have been used to flatten wire-sawn wafers. Although grinding is not as effective as lapping in removing waviness, it has many other advantages over lapping (such as higher throughput, fully automatic, and more benign to environment) and has great potential to reduce manufacturing cost of silicon wafers. This paper presents a finite element analysis (FEA) study on grinding and lapping of wire-sawn silicon wafers. An FEA model is first developed to simulate the waviness deformation of wire-sawn wafers in grinding and lapping processes. It is then used to explain how the waviness is removed or reduced by lapping and grinding and why the effectiveness of grinding in removing waviness is different from that of lapping. Furthermore, the model is used to study the effects of various parameters including active-grinding-zone orientation, grinding force, waviness wavelength, and waviness height on the reduction and elimination of waviness. Finally, the results of pilot experiments to verify the model are discussed.

关键词： finite element analysis grinding lapping silicon wafer waviness removal

ICP-MS法定量分析硅片表面金属杂质含量

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ICP-MS法定量分析硅片表面金属杂质含量