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Implementing a 1GHz Four-Issue out-of-order execution Microprocessor in a Standard Cell ASIC Methodology

Journal of Computer Science & Technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

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EBCache:A Novel Cache-Based Mechanism for Mitigating the Spectre Attacks for RISC-V Processor

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China Communications 2024年第12期21卷 166-185页

作者： Wu Dehua Xiao Wan’ang Gao Wanlin Key Laboratory of Agricultural Informatization Standardization Ministry of Agriculture and Rural AffairsChina Agricultural UniversityBeijing 100083China College of Information and Electrical Engineering China Agricultural UniversityBeijing 100083China Institute of Semiconductors Chinese Academy of SciencesBeijing 100083China Center of Materials Science and Optoelectronics Engineering&School of Microelectronics University of Chinese Academy of SciencesBeijing 100049China

The cache-based covert channel is one of the common vulnerabilities exploited in the Spectre *** mitigation strategies focus on blocking the eviction-based channel by using a random/encrypted mapping function to translate memory address to the cache address,while the updated-based channel is still *** addition,some mitigation strategies are also costly as it needs software and hardware *** this paper,our objective is to devise low-cost,comprehensive-protection techniques for mitigating the Spectre *** proposed a novel cache structure,named EBCache,which focuses on the RISC-V processor and applies the address encryption and blacklist to resist the Spectre *** addresses encryption mechanism increases the difficulty of pruning a minimal eviction *** blacklist mechanism makes the updated cache lines loaded by the malicious updates *** experiments demonstrated that the EBCache can prevent malicious *** EBCache,however,reduces the processor’s performance by about 23%but involves only a low-cost modification in the hardware.

关键词： cache structure out-of-order execution side-channel attacks the Spectre attacks

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Microarchitecture of the Godson-2 Processor

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Journal of Computer Science & Technology 2005年第2期20卷 243-249页

作者： Wei-WuHu Fu-XinZhang Zu-SongLi InstituteofComputingTechnology ChineseAcademyofSciencesBeijing100080P.R.China

The Godson project is the first attempt to design high performancegeneral-purpose microprocessors in China. This paper introduces the microarchitecture of theGodson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implementsthe 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order executiontechniques (such as register mapping, branch prediction, and dynamic scheduling) and cachetechniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps theGodson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processorhas been physically implemented on a 6-metal 0.18 μm CMOS technology based on the automaticplacing and routing flow with the help of some crafted library cells and macros. The area of thechip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3 ns.

关键词： superscalar pipeline out-of-order execution branch prediction registerrenaming dynamic scheduling non-blocking cache load speculation

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