Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

作     者：胡伟武 赵继业 钟石强 杨旭 Elio Guidetti 吴永强 

作者机构：Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland 

出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报（英文版）)

年 卷 期：2007年第22卷第1期

页      面：1-14页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Supported by the National Natural Science Foundation of China for Distinguished Young Scholars under Grant No. 60325205  the National Natural Science Foundation of China under Grant No. 60673146  the National High Technology Development 863 Program of China under Grants No. 2002AAl10010  No. 2005AAl10010  No. 2005AAl19020  and the National Grand Fundamental Research 973 Program of China under Grant No. 2005CB321600 

主　　题：general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation 

摘      要：This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.