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low-power Digital circuit Design with Triple-Threshold Voltage

Journal of Energy and power Engineering 2010年第9期4卷 56-59页

作者： J.B. Kim Department of Electronics Engineering Kangwon National University Chuncheon Kangwon 200-701 Korea

Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

关键词： low-power circuit triple-threshold CMOS circuit carry look-ahead adder very large scale integrated circuit.

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low-power MCML circuit with Sleep-Transistor

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Journal of Energy and power Engineering 2010年第7期4卷 55-59页

作者： J.B. Kim Department of Electronics Engineering Kangwon National University Chuncheon Kangwon 200-701 Korea

This paper proposes a low-power MOS current mode logic （MCML） circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The 16× 16 bit parallel multiplier is designed with the proposed technology. Comparing with the previous MCML circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/258. This circuit is designed with Samsung 0.35 um complementary metal oxide semiconductor （CMOS） process. The validity and effectiveness are verified through the HSPICE simulation.

关键词： MOS current mode logic (MCML) low-power circuit sleep-transistor multiplier very large scale integrated circuit.

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Design of a low-power CMOS LVDS I/O Interface circuit

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Journal of Energy and power Engineering 2015年第12期9卷 1101-1106页

作者： Jeong Beom Kim Department of Electronics Engineering Kangwon National University Chuncheon 24341 Republic of Korea

The paper presents the design and implementation of LVDS （low-voltage differential signaling） receiver circuit, fully compatible with LVDS standard. The proposed circuit is composed of the telescopic amplifier and the comparator with internal hysteresis. The receiver supports 3.5 Gbps data rate with 7.4 mA current at 1.8 V supply according to post-layout circuit simulations. The circuit has the power consumption of 13.1 MW. Comparing with the conventional circuit, the circuit is achieved to reduce the power consumption by 19.1% and the data rate by 14.3 %. The validity and effectiveness of the proposed circuit are verified through the circuit simulation with Samsung 0.18 μm CMOS （complementary metal-oxide-semiconductor） standard technology under the 1.8 V supply voltage.

关键词： low-power circuit LVDS interface circuit CMOS high-speed circuit telescopic amplifier

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