Low-Power Digital Circuit Design with Triple-Threshold Voltage

作     者：J.B. Kim 

作者机构：Department of Electronics Engineering Kangwon National University Chuncheon Kangwon 200-701 Korea 

出 版 物：《Journal of Energy and Power Engineering》 (能源与动力工程（美国大卫英文）)

年 卷 期：2010年第4卷第9期

页      面：56-59页

学科分类：080903[工学-微电子学与固体电子学] 080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 080502[工学-材料学] 

主　　题：Low-power circuit triple-threshold CMOS circuit carry look-ahead adder very large scale integrated circuit. 

摘      要：Triple-threshold CMOS technique provides the transistors that have low-, normal-, and high-threshold voltage. This paper describes a low-power carry look-ahead adder with triple-threshold CMOS technique. While the low-threshold voltage transistors are used to reduce the propagation delay time in the critical path, the high-threshold voltage transistors are used to reduce the power consumption in the shortest path. Comparing with the conventional CMOS circuit, the circuit is achieved to reduce the power consumption by 14.71% and the power-delay-product by 16.11%. This circuit is designed with Samsung 0.35 um CMOS process. The validity and effectiveness are verified through the HSPICE simulation.