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hardware security for IoT in the Quantum Era: Survey and Challenges

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Journal of Information security 2023年第4期14卷 227-249页

作者： Doudou Dione Boly Seck Idy Diop Pierre-Louis Cayrel Demba Faye Ibrahima Gueye IT Engineering Department Cheikh Anta Diop University Dakar Senegal

The Internet of Things (IoT) has become a reality: Healthcare, smart cities, intelligent manufacturing, e-agriculture, real-time traffic controls, environment monitoring, camera security systems, etc. are developing services that rely on an IoT infrastructure. Thus, ensuring the security of devices during operation and information exchange becomes a fundamental requirement inherent in providing safe and reliable IoT services. NIST requires hardware implementations that are protected against SCAs for the lightweight cryptography standardization process. These attacks are powerful and non-invasive and rely on observing the physical properties of IoT hardware devices to obtain secret information. In this paper, we present a survey of research on hardware security for the IoT. In addition, the challenges of IoT in the quantum era with the first results of the NIST standardization process for post-quantum cryptography are discussed.

关键词： IoT hardware security Side-Channel Attacks Post-Quantum Cryptography NIST

Identification of Important FPGA Modules Based on Complex Network

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Computers, Materials & Continua 2024年第1期78卷 1027-1047页

作者： Senjie Zhang Jinbo Wang Shan Zhou Jingpei Wang Zhenyong Zhang Ruixue Wang School of Aeronautics and Astronautics University of Chinese Academy of SciencesBeijing101408China Technology and Engineering Center for Space Utilization Chinese Academy of SciencesBeijing100094China College of Control Science and Engineering Zhejiang UniversityHangzhou310063China College of Computer Science and Technology Guizhou UniversityGuiyang550025China

The globalization of hardware designs and supply chains,as well as the integration of third-party intellectual property(IP)cores,has led to an increased focus from malicious attackers on computing ***,existing defense or detection approaches often require additional circuitry to perform security verification,and are thus constrained by time and resource *** the scale of actual engineering tasks and tight project schedules,it is usually difficult to implement designs for all modules in field programmable gate array(FPGA)*** studies have pointed out that the failure of key modules tends to cause greater damage to the ***,under limited conditions,priority protection designs need to be made on key modules to improve protection *** have conducted research on FPGA designs including single FPGA systems and multi-FPGA systems,to identify key modules in FPGA *** the single FPGA designs,considering the topological structure,network characteristics,and directionality of FPGA designs,we propose a node importance evaluationmethod based on the technique for order preference by similarity to an ideal solution(TOPSIS)***,for the multi-FPGA designs,considering the influence of nodes in intra-layer and inter-layers,they are constructed into the interdependent network,and we propose a method based on connection strength to identify the important ***,we conduct empirical research using actual FPGA designs as *** results indicate that compared to other traditional indexes,node importance indexes proposed for different designs can better characterize the importance of nodes.

关键词： hardware security FPGA circuits node importance interdependent network

Spear and Shield： Evolution of Integrated Circuit Camouflaging

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Journal of Computer Science & Technology 2018年第1期33卷 42-57页

作者： Xue-Yan Wang Qiang Zhou Yi-Ci Cai Gang Qu Department of Computer Science and Technology Tsinghua University Beijing 100083 China Department of Electrical and Computer Engineering UniversiLy of Maryland College Park MD 20740 U.S.A.

Intellectual property （IP） protection is one of the hardcore problems in hardware security. Semiconductor industry still lacks effective and proactive defense to shield IPs from reverse engineering （RE） based attacks. Integrated circuit （IC） camouflaging technique fills this gap by replacing some conventional logic gates in tile IPs with specially designed logic cells （called camouflaged gates） without changing the functions of tile IPs. The camouflaged gates can perform different logic functions while maintaining an identical look to RE attackers, thus preventing them from obtaining the layout information of the IP directly from RE tools. Since it was first proposed in 2012, circuit camouflaging has become one of the hottest research topics in hardware security focusing on two fundamental problems. How to choose the types of camouflaged gates and decide where to insert them in order to simultaneously minimize the performance overhead and optimize the RE complexity？ How can an attacker de-camouflage a camouflaged circuit and complete the RE attack？ In this article, we review the evolution of circuit camouflaging through this spear and shield race. First, we introduce the design methods of four different kinds of camouflaged ceils based on true/dummy contacts, static random access memory （SRAM）, doping, and emerging devices, respectively. Then we elaborate four representative de-camouflaging attacks： brute force attack, IC testing based attack, satisfiability-based （SAT-based） attack, and the circuit partition based attack, and the corresponding countermeasures： clique-based camouflaging, CamoPerturb, AND-tree camouflaging, and equivalent class based camouflaging, respectively. We argue that the current research efforts should be on reducing overhead introduced by circuit camouflaging and defeating decamouflaging attacks. We point out that exploring features of emerging devices could be a promising direction. Finally, as a complement to circuit camouflaging, we concl

关键词： circuit camouflaging reverse engineering intellectual property (IP) protection hardware security

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption

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Journal of Computer Science & Technology 2021年第5期36卷 1102-1117页

作者： Yi Zhong Jian-Hua Feng Xiao-Xin Cui Xiao-Le Cui Institute of Microelectronics Peking UniversityBeijing 100871China Key Laboratory of Integrated Microsystems Peking University Shenzhen Graduate SchoolShenzhen 518055China

hardware security remains as a major concern in the circuit design *** block based encryption has been widely adopted as a simple but effective protection *** this paper,the potential threat arising from the rapidly developing field,i.e.,machine learning,is *** illustrate the challenge,this work presents a standard attack paradigm,in which a three-layer neural network and a naive Bayes classifier are utilized to exemplify the key-guessing attack on logic *** with validation results obtained from both combinational and sequential benchmarks,the presented attack scheme can specifically accelerate the decryption process of partial keys,which may serve as a new perspective to reveal the potential vulnerability for current anti-attack designs.

关键词： hardware security logic encryption machine learning neural network naive Bayes classifier

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function

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Journal of Computer Science & Technology 2016年第1期31卷 124-136页

作者： Ji-Liang Zhang Qiang Wu Yi-Peng Ding Yong-Qiang Lv Qiang Zhou Zhi-Hua Xia Xing-Ming Sun Xing-Wei Wang Software College Northeastern University Shenyang 110819 China College of Information Science and Engineering Hunan University Changsha 410082 China School of Physics and Electronics Central South University Changsha 410083 China Research Institute of Information Technology Tsinghua University Beijing 100084 China School of Computer and Software Nanjing University of Information Science and Technology Nanjing 210044 China

Physical unclonable function （PUF） makes use of the uncontrollable process variations during the production of IC to generate a unique signature for each IC. It has a wide application in security such as FPGA intellectual property （IP） protection, key generation and digital rights management. Ring oscillator （RO） PUF and Arbiter PUF are the most popular PUFs, but they are not specially designed for FPGA. RO PUF incurs high resource overhead while obtaining less challenge-response pairs, and requires ＂hard macros＂ to implement on FPGAs. The arbiter PUF brings low resource overhead, but its structure has big bias when it is mapped on FPGAs. Anderson PUF can address these weaknesses of current Arbiter and RO PUFs implemented on FPGAs. However, it cannot be directly implemented on the new generation 28 nm FPGAs. In order to address these problems, this paper designs and implements a delay-based PUF that uses two LUTs in an SLICEM to implement two 16-bit shift registers of the PUF, 2-to-1 multiplexers in the carry chain to implement the multiplexers of the PUF, and any one of the 8 flip-flops to latch 1-bit PUF signatures. The proposed delay-based PUF is completely realized on 28 nm commercial FPGAs, and the experimental results show its high uniqueness, reliability and reconfigurability. Moreover, we test the impact of aging on it, and the results show that the effect of aging on the proposed PUF is insignificant, with only 6% bit-flips. Finally, the prospects of the proposed PUF in the FPGA binding and volatile key generation are discussed.

关键词： physical unclonable function (PUF) FPGA intellectual property protection fabrication variation hardware security

Enhancing security of FPGA-Based Embedded Systems with Combinational Logic Binding

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Journal of Computer Science & Technology 2017年第2期32卷 329-339页

作者： Ji-Liang Zhang Wei-Zheng Wang Xing-Wei Wang Zhi-Hua Xia Software College Northeastern University Shenyang 110169 China Key Laboratory of Computer Network and Information Integration (Southeast University) Ministry of Education Nanjing 210096 China Department of Computer and Communication Engineering Changsha University of Science and Technology Changsha 410014 China School of Computer and Software Nanjing University of Information Science and Technology Nanjing 210044 China

With the increasing use of field-programmable gate arrays （FPGAs） in embedded systems and many embedded applications, the failure to protect FPGA-based embedded systems from cloning attacks has brought serious losses to system developers. This paper proposes a novel combinational logic binding technique to specially protect FPGA-based embedded systems from cloning attacks and provides a pay-per-device licensing model for the FPGA market. security analysis shows that the proposed binding scheme is robust against various types of malicious attacks. Experimental evaluations demonstrate the low overhead of the proposed technique.

关键词： cloning attack reverse engineering FPGA (field-programmable gate array) security hardware security

Trusted Integrated Circuits: The Problem and Challenges

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Journal of Computer Science & Technology 2014年第5期29卷 918-928页

作者：吕勇强周强蔡懿慈屈钢 Tsinghua National Laboratory for Information Science and Technology Research Institute of Information Technology Tsinghua University Department of Computer Science and Technology Tsinghua University Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 U.S.A. Senior MemberIEEE

hardware security has become more and more important in current information security architecture. Recently collected reports have shown that there may have been considerable hardware attacks prepared for possible military usage from all over the world. Due to the intrinsic difference from software security, hardware security has some special features and challenges. In order to guarantee hardware security, academia has proposed the concept of trusted integrated circuits,which aims at a secure circulation of IC design, manufacture and chip using. This paper reviews the main problems of trusted integrated circuits, and concludes four key domains of the trusted IC, namely the trusted IC design, trusted manufacture,trusted IP protection, and trusted chip authentication. The main challenges in those domains are also analyzed based on the current known techniques. Finally, the main limitations of the current techniques and possible future trends are discussed.

关键词： hardware security trusted integrated circuit hardware Trojan IC authentication IP protection

A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs

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Journal of Computer Science & Technology 2014年第4期29卷 664-678页

作者：张吉良屈钢吕勇强周强 CCF ACM IEEE Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 U.S.A. College of Information Science and Engineering Hunan University Department of Computer Science and Technology Tsinghua University Research Institute of Information Technology Tsinghua University

Silicon physical unclonable function （PUF） is a popular hardware security primitive that exploits the intrinsic variation of IC manufacturing process to generate chip-unique information for various security related applications. For example, the PUF information can be used as a chip identifier, a secret key, the seed for a random number generator, or the response to a given challenge. Due to the unpredictability and irreplicability of IC manufacturing variation, silicon PUF has emerged as a promising hardware security primitive and gained a lot of attention over the past few years. In this article, we first give a survey on the current state-of-the-art of silicon PUFs, then analyze known attacks to PUFs and the countermeasures. After that we discuss PUF-based applications, highlight some recent research advances in ring oscillator PUFs, and conclude with some challenges and opportunities in PUF research and applications.

关键词： physical unclonable function hardware security trusted IC VLSI FPGA

A PUF-Based and Cloud-Assisted Lightweight Authentication for Multi-Hop Body Area Network

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Tsinghua Science and Technology 2021年第1期26卷 36-47页

作者： Wang Xiao Tan Jiliang Zhang Yuanjing Zhang Zheng Qin Yong Ding Xingwei Wang the College of Computer Science and Electronic Engineering Hunan UniversityChangsha 410082China Cyberspace security Research Center Peng Cheng LaboratoryShenzhen 518000China Guangxi Key Laboratory of Cryptography and Information security Guilin University of Electronic TechnologyGuilin 541004China the College of Computer Science and Engineering Northeastern UniversityShenyang 110004China

Wireless sensor technology plays an important role in the military,medical,and commercial fields *** Body Area Network(WBAN)is a special application of the wireless sensor network in human health monitoring,through which patients can know their physical condition in real time and respond to emergencies on *** reliability,guaranteed by the trust of nodes in WBAN,is a prerequisite for the effective treatment of ***,authenticating the sensor nodes and the sink nodes in WBAN is *** paper proposes a lightweight Physical Unclonable Function(PUF)-based and cloud-assisted authentication mechanism for multi-hop body area networks,which compared with the star single-hop network,can enhance the adaptability to human motion and the integrity of data *** authentication mechanism can significantly reduce the storage overhead and resource loss in the data transmission process.

关键词： Physical Unclonable Function(PUF) hardware security Wireless Body Area Network(WBAN)