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CADSE： communication aware design space exploration for efficient run-time MPSoC management

Frontiers of Computer Science 2013年第3期7卷 416-430页

作者： Amit Kumar SINGH Akash KUMAR Jigang WU Thambipillai SRIKANTHAN Department of Electrical and Computer Engineering National University of Singapore Singapore 119077 Singapore School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin 300160 China School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore

Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip （MPSoC）. Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisity their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources＇ status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration （CADSE） techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.

关键词： multiprocessor systems-on-chip design space exploration run-time mapping synchronous dataflow graphs throughput

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An efficient binary programming method for black-box optimization and its application in processor design

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Science China(Information Sciences) 2024年第12期67卷 140-156页

作者： Xiaoliang LV Qiaozhu ZHAI Jianchen HU Yuhang ZHU Jinhui LIU Xiaohong GUAN Faculty of Electronic and Information Engineering Xi'an Jiaotong University Department of Automation Tsinghua University

Optimizing the parameter settings in a large design space for the processor with limited simulation resources is a challenging task. The current black-box optimization algorithms for processor design space exploration(DSE) problems usually require a large amount of simulation resources for high-dimensional and discrete problems. Besides, the constraints handling techniques in these algorithms need to be improved. To address the issues, we propose an efficient binary integer programming(BIP) approach for the DSE of the processor with strictly guaranteed constraints. Our approach involves adopting the separability assumption to establish a surrogate objective function that is ordinal consistent, thus avoiding the complex non-linearity of the real objective function. Moreover, the design rules can be taken simply as constraints in BIP model to further reduce the design space. Thus, the efforts spent in the infeasible exploration space can be *** experimental results show that the proposed algorithm outperforms the state-of-the-art Bayesian optimization and evolutionary algorithms in terms of exploration efficiency, required simulation points and performance of the recommended points.

关键词： black-box optimization binary programming design space exploration processor design expensive simulation system

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