CADSE： communication aware design space exploration for efficient run-time MPSoC management

作     者：Amit Kumar SINGH Akash KUMAR Jigang WU Thambipillai SRIKANTHAN 

作者机构：Department of Electrical and Computer Engineering National University of Singapore Singapore 119077 Singapore School of Computer Science and Software Engineering Tianjin Polytechnic University Tianjin 300160 China School of Computer Engineering Nanyang Technological University Singapore 639798 Singapore 

出 版 物：《Frontiers of Computer Science》 (中国计算机科学前沿（英文版）)

年 卷 期：2013年第7卷第3期

页      面：416-430页

核心收录：

学科分类：0810[工学-信息与通信工程] 12[管理学] 083001[工学-环境科学] 0830[工学-环境科学与工程（可授工学、理学、农学学位）] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 0808[工学-电气工程] 08[工学] 0701[理学-数学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：The authors would like to thank the reviewers for their feedback and suggestions. We also wish to mention that this work is partly supported by Singapore Ministry of Education Academic Research Fund Tier 1 (R-263-000-655-133) and National Natural Science Foundation of China (NSFC) (Grant No. 61173032) 

主　　题：multiprocessor systems-on-chip design space exploration run-time mapping synchronous dataflow graphs throughput 

摘      要：Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip （MPSoC）. Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisity their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources＇ status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration （CADSE） techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.